Dynamic Clock Generation Control in Hardware Emulation
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Solution Overview
Problem
Current hardware emulation techniques for complex SoC designs are hindered by slow execution speeds and high power consumption, particularly due to manual and time-consuming clock generation and distribution methods, which do not efficiently manage asynchronous clocks and power usage.
Innovation Solution
The method involves analyzing circuit designs to determine clock-enabling functions and generating clock status signals to automatically control clock generation in emulation systems, using clock-gating and clock-selecting devices to optimize clock distribution and reduce power consumption by accelerating active clock signals during inactive periods.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If manual clock generation and distribution methods are used in hardware emulation, then clock distribution can be controlled, but emulation execution speed is slow and productivity is reduced
Solution Approach 1:
The system automatically determines clock-enabling functions by analyzing the circuit design and generates clock status signals without manual intervention. The clock generator autonomously controls clock signal generation based on the emulation state, eliminating the need for manual software codes and time-consuming execution while improving both speed and productivity
Solution Approach 2:
The system continuously monitors the emulation state and uses this feedback to dynamically control clock generation. By determining clock-enabling functions from circuit analysis and generating clock status signals based on emulation state, the system creates a closed-loop control mechanism that optimizes clock distribution in real-time, resolving the contradiction between controlled distribution and execution speed
2Use of energy by stationary object
If all clock signals are generated continuously in hardware emulation, then clock distribution is simplified, but power consumption increases
Solution Approach 1:
The system dynamically controls clock signal generation by determining clock-enabling functions and generating clock status signals that adapt to the current emulation state. This dynamic approach enables the clock generator to activate or deactivate clock signals as needed, reducing power consumption while managing complexity through systematic control mechanisms
Solution Approach 2:
The system applies different clock generation strategies to different clock domains based on their specific requirements. By determining individual clock-enabling functions for each clock signal and generating corresponding clock status signals, the system optimizes power consumption locally for each clock domain rather than applying a uniform approach, thereby reducing overall power consumption without excessive complexity
3Use of energy by stationary object
If manual clock control through software codes is used, then power consumption can be reduced by shutting off inactive clocks, but execution time increases
Solution Approach 1:
The system automatically determines clock-enabling functions by analyzing the circuit design and generates clock status signals based on the emulation state without requiring manual software codes. This self-service approach eliminates time-consuming manual execution while maintaining the power-saving benefit of shutting off inactive clocks, simultaneously addressing both power consumption and execution time
Solution Approach 2:
The system performs preliminary analysis of the circuit design to determine clock-enabling functions before emulation begins. By pre-determining which clocks should be enabled under different conditions and generating相应的 clock status signals, the system prepares the clock control mechanism in advance, eliminating the need for time-consuming manual software codes during actual emulation while maintaining power efficiency
Data Source
AI summary
Aspects of the invention relate to techniques for dynamic control of design clock generation in emulation. A circuit design for verification is analyzed to determine one or more clock-enabling functions for a specific clock signal. Logic for generating a clock status signal based on the one or more clock-enabling signals is then determined. The clock status signal is employed to control clock generation in an emulation system for emulating the circuit design.