Dynamic Clock Frequency Adjustment for Waiting Multiprocessor Cores
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Solution Overview
Problem
Multiprocessor systems face high power consumption due to high operating frequencies, especially when processors are waiting for other devices, leading to significant battery usage without adding value in processing.
Innovation Solution
Implementing a method where waiting processors reduce their operating frequency to a fraction of the normal frequency when in a wait loop for an extended period, monitored by a loop count threshold, and revert to normal frequency when no longer waiting, using a loop count monitor, frequency adjuster, and availability monitor within the system.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If processors operate at high frequencies to achieve fast processing speeds, then processing throughput is improved, but power consumption increases
Solution Approach 1:
The patent applies dynamics by making the processor frequency adjustable rather than fixed. The frequency is dynamically changed based on whether the processor is in a waiting state or actively processing. When waiting for data from another processor, the frequency is reduced to a lower level; when data is available and processing can proceed, the frequency is increased to a higher level. This dynamic frequency adjustment allows the system to optimize between power consumption and processing throughput depending on the operational state.
Solution Approach 2:
The patent changes the operating parameter (clock frequency) of the processor based on its operational state. Specifically, the frequency parameter is modified from a high value during active processing to a low value during waiting periods. This parameter change directly addresses the contradiction by reducing power consumption when high processing throughput is not needed, while maintaining high throughput capability when data is available for processing.
2Reliability
If processors wait for data from other processors, then data availability is improved, but power consumption increases due to high frequency operation during idle periods
Solution Approach 1:
The system dynamically adjusts processor frequency based on whether the processor is in a waiting state or actively processing. When a processor is waiting for data from another processor, the frequency is reduced to a lower level, thereby reducing power consumption during idle periods while still maintaining the ability to quickly resume high-speed operation when data becomes available.
Solution Approach 2:
The clock frequency parameter is changed based on the operational state of the processor. During waiting periods when data availability is the primary concern, the frequency is lowered to reduce power consumption. When data is available and the processor can proceed with processing, the frequency is increased to maintain high throughput. This parameter change resolves the contradiction between ensuring data availability and minimizing power consumption during waiting states.
Data Source
AI summary
Methods and apparatus provide for reducing power consumption by decreasing operating frequencies of waiting processors in a multiprocessor system. Power consumption may be reduced by having a processor enter a low frequency mode when the processor is in a loop waiting for data that have been locked by another processor. The frequency of operation of the waiting processor may be reduced to a fraction (one half, one quarter, etc.) of the normal, initial clock frequency. The multiprocessor system may monitor a number of times (loop count) that a waiting processor takes the wait loop and compare the number to a threshold. When the loop count is greater than or equal to the threshold, the clock frequency of the waiting processor is reduced. When the waiting processor ceases to wait and does not take the wait loop branch (e.g., because the other processor has released the lock on the data), the loop count is reset to zero and the frequency of operation of waiting processor is increased to an increased frequency, such as the normal, initial level.