Dynamic Clock Frequency Adjustment via Buffer Utilization Monitoring
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Solution Overview
Problem
The increasing power consumption in network switching chips due to higher clock frequencies leads to increased dynamic power consumption, which is proportional to the switching activities of the circuit, necessitating a reduction in clock frequency without sacrificing data packet processing performance.
Innovation Solution
A controller monitors the upstream buffer utilization and adjusts the clock signal frequency by increasing or decreasing the number of clock edges based on buffer utilization thresholds, using techniques like clock gating to optimize power consumption while preventing buffer overflow.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If clock frequency is increased to handle additional packets, then data processing capability is improved, but power consumption increases
Solution Approach 1:
The patent implements dynamic clock frequency adjustment based on buffer utilization levels. The system transitions from a fixed clock frequency to a dynamic one that adapts to actual processing needs, allowing the clock frequency to increase when buffer utilization is high and decrease when buffer utilization is low, thus resolving the contradiction between processing capability and power consumption
Solution Approach 2:
The patent changes the clock frequency parameter dynamically based on buffer utilization characteristics. By monitoring buffer utilization and adjusting the clock frequency accordingly, the system optimizes the balance between data processing capability and power consumption, transforming a static parameter into a dynamic one that responds to system conditions
2Use of energy by moving object
If clock frequency is reduced to lower power consumption, then power consumption is reduced, but data packet processing performance deteriorates
Solution Approach 1:
The patent implements a feedback mechanism where buffer utilization characteristics are continuously monitored and used to adjust clock frequency. This feedback loop ensures that the clock frequency is reduced only when buffer utilization is low, preventing performance deterioration while still achieving power savings, thus resolving the contradiction between power consumption and processing performance
3Use of energy by moving object
If clock frequency is dynamically adjusted based on buffer utilization, then power consumption is reduced, but system complexity increases
Solution Approach 1:
The patent implements self-service by allowing the system to automatically monitor its own buffer utilization and adjust clock frequency without external intervention. The system serves itself by using its own operational state (buffer utilization) to control its own performance characteristics (clock frequency), reducing the need for complex external control mechanisms while still achieving dynamic power optimization
Data Source
AI summary
The embodiments disclosed herein provide a computing device that includes an upstream buffer and downstream data processing circuit that establish a data processing path where the data stored by upstream buffer is received and processed by the downstream data processing circuit. Using a buffer utilization characteristic of the upstream buffer such as its current availability (e.g., the buffer is 50% full) or an input data rate, the computing device adjusts the clock signal used to drive the downstream data processing circuit. For example, if the utilization of the upstream buffer is low, the number of clock edges in the clock signal may be reduced thereby reducing power consumption of the computing device. However, as the utilization of the buffer begins to increase, the computing device may increase the number of clock edges to prevent a buffer overflow.