Dynamic Clock Frequency Control for Parallel Processing Modules
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Solution Overview
Problem
Existing techniques face challenges in accurately controlling clock signal frequencies and power source voltages in processing modules, especially when processing times vary due to input data, leading to inefficiencies in parallel processing systems.
Innovation Solution
An information processing apparatus with multiple processing units that estimate processing times based on evaluation values from adjacent modules, adjusting clock signal frequencies accordingly to synchronize processing times and reduce power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a fixed clock signal frequency is supplied to all processing modules, then system simplicity is maintained, but processing efficiency decreases when processing times vary
Solution Approach 1:
The patent implements dynamic clock frequency adjustment where each processing module's clock signal frequency is varied based on its current processing load and estimated processing time. The clock control unit continuously monitors processing status and adjusts frequencies in real-time, transforming a static system into a dynamic one that adapts to changing conditions, thereby resolving the contradiction between maintaining simplicity and improving efficiency.
Solution Approach 2:
The invention changes the parameter of clock signal frequency from a fixed value to a variable parameter that is adjusted according to processing requirements. By modifying this key parameter dynamically based on processing time estimates and evaluation values, the system achieves higher processing efficiency without requiring complete system redesign.
2Productivity
If clock signal frequency is increased to reduce processing time, then processing speed improves, but power consumption increases
Solution Approach 1:
The patent optimizes the clock signal frequency parameter by adjusting it to match actual processing requirements rather than using a consistently high frequency. The clock control unit determines appropriate frequencies based on evaluation values and processing time estimates, ensuring that processing speed is sufficient while avoiding unnecessary energy consumption from excessively high frequencies when not needed.
Solution Approach 2:
Instead of applying maximum clock frequency to all modules continuously, the system applies partial action by adjusting frequencies individually based on actual processing needs. Modules requiring faster processing receive higher frequencies, while others operate at lower frequencies, avoiding the excessive energy consumption that would result from uniform high-frequency operation across all modules.
3Loss of energy
If clock signal frequency is dynamically adjusted based on processing status, then energy efficiency improves, but control complexity increases
Solution Approach 1:
Each processing module autonomously calculates its own evaluation value and estimated processing time based on its current processing status. The modules self-regulate their resource requirements without requiring complex centralized control, thereby improving energy efficiency while minimizing the complexity of the control mechanism through decentralized decision-making.
Solution Approach 2:
The system implements feedback loops where processing modules continuously report their status and receive adjusted clock frequencies in response. The clock control unit uses evaluation values and processing time estimates as feedback to dynamically adjust frequencies, creating a closed-loop control system that improves energy efficiency through responsive adjustment rather than complex open-loop control mechanisms.
Data Source
AI summary
An information processing apparatus includes a plurality of processing units each configured to execute predetermined processing on input data in parallel and calculate an evaluation value based on the executed processing, an estimation unit configured to perform estimation of a processing time required for each of the plurality of the processing units to perform the predetermined processing based on the evaluation values calculated by the relevant processing unit and at least one other processing unit of the plurality of the processing units, and a clock control unit configured to, with respect to each of the processing units, determine a frequency of a clock signal to be supplied to the relevant processing unit in response to the estimated processing time of the relevant processing unit and supply the clock signal having the determined frequency.