Dynamic Clock Frequency Control for Low Power Systems
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Solution Overview
Problem
Computer systems face inefficiencies in reducing power consumption while maintaining performance, as lowering the core clock frequency in cascading clock arrangements affects system bus and peripheral clocks, leading to potential performance degradation and requiring complex reprogramming.
Innovation Solution
Incorporating programmable clock dividers and switches that allow independent adjustment of core, system bus, and peripheral clock frequencies, enabling operation in low-power mode without altering downstream clock frequencies, thus reducing power consumption without performance tradeoffs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the core clock frequency is reduced to lower power consumption, then power consumption is reduced, but the system bus and peripheral clocks are also slowed down causing performance degradation
Solution Approach 1:
The patent segments the clock distribution system by introducing independent clock buffers for the core clock, system bus clock, and peripheral clock. This allows each clock domain to be controlled independently, so the core clock can be reduced to save power while the system bus and peripheral clocks maintain their original frequencies to preserve performance.
Solution Approach 2:
The patent implements dynamic clock frequency adjustment by providing multiple operating modes (normal mode and low-power mode) that can be switched based on system conditions. In low-power mode, the core clock frequency is reduced while the system bus and peripheral clocks remain unchanged, enabling dynamic optimization of power-performance tradeoffs.
2Use of energy by moving object
If the core clock frequency is reduced in a cascading clock arrangement, then power consumption is reduced, but reprogramming the programmable divider circuit is required adding complexity
Solution Approach 1:
The patent pre-configures multiple clock buffers with different division ratios to handle various operating modes. Instead of dynamically reprogramming the programmable divider circuit when switching modes, the system can simply switch between pre-configured buffers, eliminating the need for complex reprogramming operations and reducing circuit complexity.
3Use of energy by moving object
If the core clock frequency is reduced to conserve power, then power consumption is reduced, but the system bus and peripheral operations are slowed despite being busy conducting operations
Solution Approach 1:
The patent segments the clock control into independent domains using separate clock buffers. This allows the core clock to be reduced independently without affecting the system bus and peripheral clocks, so power-saving operations can proceed while I/O operations complete at full speed without time loss.
Data Source
AI summary
Circuits for generating multiple clocks for computer systems are disclosed. One such system includes a circuit configured to generate a core clock, a system bus clock, and a peripheral clock. The frequency of one of the clocks can be reduced or altered without altering the frequencies at which the other clocks oscillate. Also disclosed are methods for incorporating or utilizing the disclosed circuits.