Dynamic Clock Gating for Core Voltage Regulation
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Solution Overview
Problem
Existing methods for regulating core activity in CPU or GPU modules suffer from performance losses due to conservative slowing down mechanisms and unpredictable automatic triggers, which can lead to voltage fluctuations and overheating, potentially causing core crashes.
Innovation Solution
A method involving a clock-gating module that monitors core voltage and adjusts the clock rate by decreasing or increasing the ratio of active cycles based on trigger values, creating a reaction loop to adapt to voltage variations while minimizing performance drops.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If progressive activation techniques are used to slow the rise of power consumption and temperature, then core stability is improved, but core performance deteriorates due to unnecessary slowdowns
Solution Approach 1:
The patent changes the control parameter from fixed progressive activation to dynamic voltage-based clock gating. The system monitors actual core voltage and adjusts clock cycles dynamically, changing parameters based on real-time conditions rather than predetermined sequences, thus maintaining stability while avoiding unnecessary performance loss
Solution Approach 2:
The patent implements a feedback mechanism where the system continuously monitors core voltage and uses this information to adjust clock gating decisions. This closed-loop control ensures that slowdowns only occur when actually needed to maintain stability, eliminating the performance loss associated with open-loop progressive activation
2Reliability
If automatic triggering techniques are used to regulate core activity, then core stability is improved, but unpredictable performance loss occurs due to unexpected triggers
Solution Approach 1:
The system uses real-time voltage monitoring feedback to determine when clock gating should be applied. This ensures that triggering is based on actual core conditions rather than external or unpredictable signals, making the regulation both stable and predictable
Solution Approach 2:
The core effectively regulates itself by monitoring its own voltage conditions and triggering clock gating only when its own parameters indicate instability risk, eliminating the need for external triggers that may be unpredictable
Data Source
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AI summary
It is proposed a method for regulating the activity of a core running at a given clock rate. The method comprises: - monitoring (S100) a value of a parameter of the core, the parameter being a critical parameter for a safe operating of the core; - determining whether the monitored value reaches a trigger value; - when the monitored value reaches the trigger value (S 120): ∘ modifying the clock rate of the core (S130) by decreasing the ratio of active cycles of the clock; and ∘ running the core at the clock rate modified (S140) by decreasing the ratio of active cycles of the clock; - when the monitored value reaches a second time the trigger value (S170): ∘ modifying the clock rate of the core (S180) by increasing the ratio of active cycles of the clock; and ∘ running the core at the clock rate (S190) modified by increasing the ratio of active cycles of the clock.