Dynamic Clock Feedback Latch for Critical-Path Delay Removal
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Solution Overview
Problem
The delay associated with static latches in dynamic logic circuits is a significant portion of the clock cycle time, limiting the processing capacity of microprocessors.
Innovation Solution
A dynamic clock feedback latch is introduced, which includes a feedback path and transistors to pre-charge and drain a node based on clock inputs, allowing for latching of data values without the delay of a conventional static latch by using a feedback path to generate a latching value after the clock goes high.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a static latch is used to latch dynamically evaluated data, then the data can be held stable, but the latch delay consumes a large proportion of the clock cycle time
Solution Approach 1:
The patent applies dynamic logic principles to the latch circuit itself, using dynamic evaluation and precharge/discharge mechanisms instead of static latch structures. The latch uses dynamic nodes that are precharged during the precharge phase and discharged during the evaluation phase, eliminating the need for static latch delay while maintaining data stability through the dynamic evaluation process.
Solution Approach 2:
The patent implements feedback paths that feed the output of the dynamic logic back to the latch input, allowing the latch to capture the dynamically evaluated data without requiring a static latch structure. The feedback mechanism ensures that the data is properly latched at the correct moment in the clock cycle, maintaining reliability while reducing delay.
2Productivity
If the clock cycle time is reduced to process more instructions per second, then productivity increases, but the latch delay becomes a larger proportion of the available time
Solution Approach 1:
By making the latch dynamic rather than static, the circuit can operate at higher frequencies without the penalty of static latch delay. The dynamic latch evaluates and latches data within the same clock cycle using precharge and evaluation phases, allowing the clock cycle time to be reduced while maintaining adequate time for data latching.
Solution Approach 2:
The patent uses periodic precharge and evaluation phases synchronized with the clock signal. During the precharge phase, nodes are prepared; during the evaluation phase, data is captured. This periodic action allows the latch to keep up with reduced clock cycle times by resetting and evaluating in rhythm with the clock, preventing latch delay from becoming a disproportionate burden.
3Speed
If dynamic logic is used in critical timing paths, then speed is improved, but the data still requires latching which introduces delay
Solution Approach 1:
The patent merges the dynamic logic evaluation and the latching functions into a single integrated structure. The output of the dynamic logic is directly fed back to the latch input, and the latch uses the same clock phases as the dynamic logic evaluation. This merging eliminates the need for a separate static latch stage, thereby eliminating the additional latching delay while preserving the speed benefits of dynamic logic.
Solution Approach 2:
The latch is made dynamic to match the dynamic nature of the logic being latched. This allows the latch to evaluate and capture data in the same time frame as the dynamic logic, rather than requiring a separate static latching phase. The dynamic latch uses precharge and evaluation phases that are synchronized with the dynamic logic, eliminating the speed penalty that would otherwise be introduced by static latching.
Data Source
AI summary
A dynamic clock feedback latch includes a feedback path that generates a data value on an output as a function of data inputs in response to a clock input going low and generates a latching value on the output after a delay from the clock input going high. A first transistor pre-charges a node high while the clock input is low. A second transistor provides a drain path for draining the node low from the pre-charged value while the clock input is high. The output controls a third transistor during the delay to drain the node to a low value if the data value is high and to retain the high value if the data value is low. The feedback path generates the predetermined latching value on the output after the delay to cause an inverted value of the data value to be latched onto the node.