Dynamic Clock Phase Control for Power Peak Smoothing
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Solution Overview
Problem
Synchronous data processing pipelines face issues with power consumption peaks that can disrupt NFC communications and are vulnerable to side channel attacks, as they do not provide sufficient protection against powerful correlation techniques based on power consumption.
Innovation Solution
A data processing pipeline with a clock controller that generates clock signals based on a master clock signal, allowing for dynamic phase control, enabling in-phase and out-of-phase timing edges to spread data processing cycles over multiple clock periods, thereby reducing power consumption peaks and enhancing security against side channel attacks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If synchronous pipeline operation is used to achieve high data processing rates, then productivity is improved, but power consumption peaks occur on each clock edge which can disrupt NFC communications
Solution Approach 1:
The pipeline stages are divided into different groups that can be clocked independently with different clock signals. This segmentation allows the clock edges to be distributed across different time periods, breaking the simultaneous power consumption peaks into smaller, staggered peaks that can be smoothed by the power supply.
Solution Approach 2:
Different clock signals with different phases and periods are applied to different pipeline stages. This creates a periodic distribution of clock edges over time, spreading the power consumption peaks across multiple clock periods rather than having them all occur simultaneously, thereby smoothing the overall power consumption profile.
2Productivity
If synchronous pipeline operation is used to achieve high data processing rates, then productivity is improved, but vulnerability to side channel attacks increases due to visible power consumption patterns
Solution Approach 1:
Asymmetric clocking is applied where different pipeline stages receive clock signals with different phases, periods, and timing characteristics. This creates an asymmetric power consumption pattern that does not directly correlate with the processed data in a predictable manner, making correlation-based side channel attacks less effective.
Solution Approach 2:
The clock signals are dynamically configured with variable phases and periods that can be adjusted during operation. This dynamic clocking strategy changes the timing characteristics of power consumption over time, preventing attackers from establishing stable correlation models between power consumption and processed data.
3Use of energy by moving object
If clock rate is reduced to lower power consumption in NFC cards, then use of energy is improved, but current consumption peaks become more pronounced and visible at the antenna
Solution Approach 1:
The power consumption is segmented across multiple clock periods by distributing clock edges to different pipeline stages at different times. This segmentation prevents the aggregation of current peaks that would otherwise be visible at the antenna, even at lower clock rates.
Solution Approach 2:
The clock signal parameters (phase, period, frequency) are changed dynamically to optimize the distribution of power consumption. By adjusting these parameters, the system can maintain lower overall power consumption while ensuring that current peaks are sufficiently distributed and smoothed to avoid antenna visibility issues.
Data Source
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AI summary
The invention concerns a data processing pipeline comprising: first and second pipeline stages (302, 304) respectively receiving first and second clock signals (CLKO, CLK1) and configured to perform first and second operations respectively triggered by first timing edges of the first clock signal (CLK0) and second timing edges of the second clock signal (CLK1) ; and a clock controller configured to generate the first and second clock signals (CLKO, CLK1) and being capable of operating: in a first mode in which, during a first data processing cycle of the data processing pipeline, a first of the first timing edges is in-phase with a first of the second timing edges; and in a second mode in which, during a second data processing cycle of the data processing pipeline, a second of the first timing edges is out of phase with a second of the second timing edges.