Dynamic Clock Rate Adjustment for Power Control in Computer Systems

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Solution Overview

Problem

Traditional computer systems waste power by setting a maximum clock rate for processing units based on peak MIPS requirements, leading to inefficiency when actual MIPS demands are lower.

Innovation Solution

A power control device and method that adjust the clock rate of internal elements like data processing units, output buffers, and input buffers by monitoring data output rates and comparing them to predetermined thresholds, allowing for dynamic clock rate adjustments to match varying processing demands.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the maximum clock rate is set for the processing unit based on maximum MIPS requirements, then the system can handle peak processing demands, but power consumption increases when actual MIPS requirements are lower

Engineering Contradiction:
Improveprocessing capabilityVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent implements dynamic clock rate adjustment by introducing a throughput determining module that continuously monitors data output rates and compares them with predetermined thresholds. Based on these comparisons, the clock control unit dynamically adjusts the clock rate of the processing unit, transitioning from a static maximum clock rate to a dynamic adaptation mechanism that matches actual processing demands, thereby resolving the contradiction between maintaining processing capability and reducing power consumption

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the operational parameter (clock rate) of the processing unit based on measured throughput conditions. By establishing multiple predetermined thresholds and corresponding clock rate levels, the system can switch between different operational states, adjusting the clock rate parameter to match actual MIPS requirements rather than always operating at maximum capacity, thus reducing power consumption while maintaining adequate processing capability

Inventive Principle:
Principle #35Parameter changes

2Use of energy by moving object

If the clock rate is reduced to save power, then power consumption decreases, but data processing throughput may be compromised

Engineering Contradiction:
Improvepower consumptionVSAvoiddata processing throughput
Core Design Contradiction:
Use of energy by moving objectVSProductivity

Solution Approach 1:

The patent implements a feedback control mechanism where the throughput determining module continuously monitors the actual data output rate of the processing unit and feeds this information back to the clock control unit. This closed-loop feedback system ensures that clock rate adjustments are based on real-time throughput measurements, allowing the system to reduce power consumption by lowering clock rates when throughput demands are low, while automatically increasing clock rates when throughput requirements rise, thus maintaining productivity

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The system performs self-adjustment of its operational parameters by autonomously monitoring its own throughput performance and automatically adjusting its clock rate accordingly. The processing unit effectively serves itself by having the throughput determining module measure its own output rate and the clock control unit adjust its own operating frequency, eliminating the need for external intervention and ensuring that power consumption is optimized while maintaining adequate throughput performance

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS8364996B2Power control device and power control method applied to computer system
Publication Date: 2013.01.29 ALI CORP
  • US8364996B2 patent drawing
  • US8364996B2 patent drawing
  • US8364996B2 patent drawing

AI summary

The present invention provides a power control device and a power control method applied to a computer system. The power control device includes a data processing unit, a throughput determining module, and a clock control unit. The data processing unit is utilized for processing and outputting data according to an adjustable clock rate. The throughput determining module is coupled to the data processing unit, and utilized for obtaining an indication value corresponding to a data output rate of the data processing unit and comparing the indication value with at least a predetermined threshold value to generate a comparing result. The clock control unit is coupled between the throughput determining module and the data processing unit, and utilized for adjusting the adjustable clock rate of the data processing unit according to the comparing result.