Dynamic Clock Scaling for Non-Volatile Storage I/O Interfaces
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Solution Overview
Problem
Current dynamic clock-voltage scaling techniques primarily focus on memory and processor subsystems, neglecting the significant power consumption of storage device I/O subsystems, which is increasing with rising clock frequencies, necessitating a method to reduce power consumption in non-volatile storage devices like SSDs and eMMC without degrading user experience.
Innovation Solution
A non-volatile storage system that dynamically adjusts the I/O interface clock frequency based on predicted load and idle time, using a frequency governor to compare these factors to thresholds, instructing a clock control block to adjust the clock signal accordingly, thereby conserving power while maintaining user experience.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If clock frequency of I/O subsystem is increased, then data transfer speed is improved, but power consumption increases
Solution Approach 1:
The patent implements dynamic clock frequency adjustment in the I/O subsystem by monitoring queue depth and transfer rates, and adjusting the clock frequency accordingly. The system transitions from static high frequency operation to dynamic frequency scaling, where the clock frequency is adjusted in real-time based on actual data transfer needs, thus reducing power consumption during low-activity periods while maintaining high speed when needed.
Solution Approach 2:
The patent changes the operational parameters of the I/O subsystem by adjusting clock frequency based on queue depth thresholds and transfer rate measurements. The system monitors the number of pending I/O requests and the actual data transfer rate, then modifies the clock frequency parameter to optimize the balance between performance and power consumption, directly addressing the contradiction between speed and energy use.
2Use of energy by moving object
If clock frequency is reduced to save power, then power consumption decreases, but user experience may be degraded
Solution Approach 1:
The patent implements a feedback mechanism that continuously monitors queue depth and data transfer rates, then uses this information to make intelligent decisions about clock frequency adjustment. The system only reduces frequency when the queue depth is below a threshold and the transfer rate indicates spare capacity, ensuring that user-performant operations are not impacted. This feedback loop prevents degradation of user experience while achieving power savings.
Solution Approach 2:
The patent applies partial frequency reduction rather than complete throttling. By adjusting the clock frequency partially based on queue depth and transfer rate conditions, the system achieves power savings without completely disabling the I/O subsystem's performance capabilities. This partial action approach ensures that when needed, the system can still deliver responsive performance, maintaining user experience while reducing overall power consumption.
Data Source
AI summary
This disclosure discusses systems, methods, and apparatus for dynamically scaling a clock frequency of an I/O interface to a non-volatile storage device. The scaling can be based on monitoring an idle time on the I/O interface, a priority of one or more applications having read/write requests queued for dispatch to the I/O interface, a load of the queued read/write requests on the I/O interface or a combination of priority and load. Such variables can be compared to thresholds in a frequency governor.