Dynamic CMOS Frequency Divider for High-Speed Low-Power Operation
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Solution Overview
Problem
Existing frequency dividers face challenges in balancing high-speed operation with low power consumption, particularly in applications involving high frequencies, as they often require either high power consumption for high-frequency operations or are limited by low power consumption for lower frequency applications.
Innovation Solution
A frequency divider design incorporating CMOS inverters connected in dynamic configurations and a cascade connection structure, which allows for direct electrical connections without intervening transistors, optimizing power supply and ground connections to achieve high-speed operation with low power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If existing frequency dividers are designed for high-frequency operations, then operating speed is improved, but power consumption increases undesirably
Solution Approach 1:
The patent applies dynamic operation by enabling the frequency divider to selectively switch between different operational modes (first mode for high-frequency division, second mode for low-frequency division) based on input conditions. This dynamic adaptability allows the circuit to optimize power consumption by using the high-speed first mode only when necessary, while utilizing the low-power second mode for standard operations, thereby resolving the contradiction between speed and power consumption
Solution Approach 2:
The patent changes operational parameters by modifying the conduction states of transistors and the activation of different circuit paths depending on the division ratio requirements. By dynamically adjusting parameters such as transistor conduction, clock signal routing, and circuit mode selection, the frequency divider achieves high-speed operation when needed while maintaining low power consumption during normal operation, effectively resolving the speed-power tradeoff
2Use of energy by moving object
If existing frequency dividers are designed for low power consumption, then power consumption is reduced, but they become inapplicable for high-frequency applications
Solution Approach 1:
The frequency divider dynamically switches between two operational modes: a first mode optimized for high-frequency operation with higher power consumption, and a second mode optimized for low-power operation. The circuit selectively activates the high-speed first mode only when high-frequency division is required, while using the low-power second mode for standard operations, thereby achieving both low power consumption and high-frequency capability when needed
3Speed
If direct electrical connections are used without intervening transistors, then power consumption is reduced and speed is improved, but circuit design complexity increases
Solution Approach 1:
The patent segments the frequency divider circuit into distinct functional blocks with clearly defined roles: a first circuit portion handling high-frequency division operations and a second circuit portion handling low-frequency division operations. This segmentation allows direct electrical connections within each segment to minimize power consumption and maximize speed, while the modular structure manages overall circuit complexity by localizing complex interconnections within specific segments rather than across the entire circuit
Data Source
AI summary
A frequency divider may include the following elements: a first inverter, a second inverter, and a third inverter, which are connected in a ring structure, wherein the second inverter is connected to an output terminal of the frequency divider; a fourth inverter connected to a first input terminal of the frequency divider and to a power supply terminal of the first inverter; a fifth inverter connected to a second input terminal of the frequency divider and to a power supply terminal of the third inverter; a first transistor connected to the second input terminal of the frequency divider and to a ground terminal of the first inverter; and a second transistor connected to the first input terminal of the frequency divider and to a ground terminal of the third inverter. The second inverter, the fourth inverter, and the fifth inverter may receive a power supply voltage.