Dynamic-Impedance CMOS Gate Drivers for Narrow GaN Pulses
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Solution Overview
Problem
Current gate driver technologies for GaN power transistors face challenges in generating narrow pulses due to external damping resistors, which slow rise/fall times and require exponential resistor counts for multiple drivers, and slope control methods are complex with feedback loops and external components, limiting high-frequency and high-power applications.
Innovation Solution
A segmented driver architecture with binary weighted drivers in parallel allows for dynamic output impedance control, subdividing logic high and low pulse durations into independent phases, eliminating the need for external components and enabling precise digital control of gate driver output.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If external damping resistors are used in gate driver technologies, then the gate driver can operate reliably, but the rise/fall times are slowed and the resistor count increases exponentially for multiple drivers
Solution Approach 1:
The patent removes external damping resistors from the gate driver system by implementing an intrinsic impedance control mechanism within the driver itself. The segmented driver architecture with binary-weighted current sources provides internal damping functionality through controlled current switching, eliminating the need for external passive components and reducing overall device complexity.
Solution Approach 2:
The patent combines multiple driver functions into a single integrated segmented driver unit. By merging the damping function, pulse generation, and impedance control into one unified structure with binary-weighted current sources, the design reduces the exponential growth of resistor counts when scaling to multiple drivers.
2Manufacturing precision
If slope control methods are used to generate narrow pulses, then pulse width control is achieved, but the circuit complexity increases with feedback loops and external components
Solution Approach 1:
The patent divides the gate driver output into multiple independent phases using binary-weighted current sources. Each segment can be independently controlled to contribute to the overall pulse shape and width, enabling precise pulse control through digital weighting factors without requiring complex analog feedback loops or external slope control components.
Solution Approach 2:
The patent implements dynamic output impedance control by digitally adjusting the weighting factors of binary-weighted current sources in real-time. This allows the driver to adaptively shape pulse edges and control pulse width dynamically, replacing static slope control circuits with flexible digital control mechanisms.
3Power
If multiple gate drivers are used to drive multiple power devices, then the power handling capability increases, but the resistor count increases exponentially
Solution Approach 1:
The patent creates a universal segmented driver architecture that can drive multiple power devices with a standardized design. Each driver unit uses the same binary-weighted current source structure, allowing scalable multiplication of power handling capability without proportional increases in external passive components, as the intrinsic impedance control is built into each modular unit.
4Productivity
If conventional gate drivers are used for high-frequency applications, then the circuit is simple, but the switching speed and EMI performance are limited
Solution Approach 1:
The patent employs periodic switching of binary-weighted current sources to generate gate drive signals at high frequencies. The segmented architecture allows each current source to switch in a coordinated periodic manner, enabling high-frequency operation with controlled EMI through the inherent damping effect of the intrinsic impedance control mechanism.
Data Source
AI summary
One aspect disclosed features an apparatus comprising: an input buffer configured to receive an input voltage pulse as an input, and to output, responsive to a leading edge of the input voltage pulse, a logic high voltage pulse at a first output of the input buffer and a logic low voltage pulse at a second output of the input buffer; an array of L active pull-up devices electrically coupled between a positive supply rail and an output node, each active pull-up device driven by the logic high voltage pulse as modulated by a corresponding bit of a series of N first L-bit binary words; and an array of L active pull-down devices electrically coupled between a negative supply rail and the output node, each active pull-down device driven by the logic low voltage pulse as modulated by a corresponding bit of a series of M second L-bit binary words.