Dynamic Code Migration Between NOR Flash and SRAM
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Heterogeneous memory systems face challenges in balancing cost, capacity, performance, and power consumption, particularly in cost-sensitive embedded systems like smart sensors and IoT devices, due to limitations in static RAM and NOR flash, where existing solutions like execution in place (XIP) result in high latency and inefficient SRAM usage.
Innovation Solution
A dynamic code execution method that uses software profiling counters to identify frequently used byte codes in NOR flash, moving them to SRAM for reduced latency and performance benefits while minimizing SRAM usage, by creating and managing an Interpreter Routine Address Table (IRIT) to dynamically schedule code execution between NOR flash and SRAM based on usage and resource efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If code is executed directly from NOR flash using execution in place (XIP), then SRAM usage is reduced, but execution latency increases significantly
Solution Approach 1:
The patent segments code into frequently used byte codes and less frequently used byte codes, storing the former in SRAM and the latter in NOR flash. This segmentation resolves the contradiction by placing only the critical time-sensitive code in fast memory while keeping overall SRAM usage low.
Solution Approach 2:
The patent implements dynamic code migration between SRAM and NOR flash based on usage frequency. Software profiling counters track byte code access patterns, and the system dynamically moves code between memory types, making the memory allocation adaptive rather than static.
2Productivity
If frequently used byte codes are moved to SRAM, then execution speed improves, but SRAM usage increases
Solution Approach 1:
The patent applies partial action by moving only the frequently used byte codes to SRAM rather than loading entire programs. The software profiling counters identify specific byte codes that benefit from fast access, and only those are migrated, achieving speed improvement with minimal SRAM consumption.
Solution Approach 2:
The system changes the parameter of memory allocation from static to dynamic based on usage frequency. The software profiling counters measure access patterns, and the migration decision is based on these measured parameters, optimizing the balance between speed and memory usage.
3Productivity
If more SRAM is allocated for code execution, then performance increases, but material cost and power consumption increase
Solution Approach 1:
The patent uses partial action by allocating SRAM only for the portion of code that is frequently executed, as identified by software profiling counters. This partial allocation achieves performance improvement for critical paths while minimizing overall SRAM usage, thereby reducing material cost and power consumption.
Solution Approach 2:
The system performs self-service through software profiling counters that automatically track byte code usage patterns and trigger migrations. This self-monitoring and self-optimizing mechanism eliminates the need for manual configuration or over-provisioning of SRAM, achieving cost-effective performance optimization.
Data Source
AI summary
Systems and techniques for dynamic code execution location in heterogeneous memory are described herein. In an system having a first class of memory and second class of memory that are both byte-addressable, an interpreter may be initialized to execute a program from the first class of memory. The initialization may include locating an Interpreter Routine Address Table (IRIT) in the second class of memory and creating counters for routines in the IRIT. A counter for a routine may be modified as it is referenced from the IRIT during execution. The routine may be moved from the first class of memory to the second class of memory in response to the counter passing a threshold. An entry in the IRIT for the routine may be updated with an address in the second class of memory corresponding to the routine.