Dynamic Column Redundancy Replacement in Flash Memory
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Solution Overview
Problem
Traditional column redundancy schemes for non-volatile memory chips require significant chip area and processing time, especially in high-density FLASH memory controllers, leading to under-utilization of controller logic and increased latency due to the need for static data processing and page buffers.
Innovation Solution
A dynamic column redundancy replacement system that includes input and output data replacement logic blocks, a column redundancy match logic block, and FIFO registers to mask and modify data on-the-fly during user operations, allowing concurrent redundancy replacement without the need for a page buffer, utilizing latency between user serial operations and memory communication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional column redundancy schemes use page buffers and multiplexers, then data can be held and processed during redundancy operations, but chip area increases significantly
Solution Approach 1:
The patent extracts the page buffer component from the redundancy system entirely. Instead of using a dedicated page buffer to hold data during redundancy operations, the system processes data directly through the serial interface, eliminating the need for large buffer memory and associated control logic on the chip.
Solution Approach 2:
The serial interface circuitry is made multi-functional by using it for both data transfer and redundancy replacement operations. The same data path and control logic that handle user data also perform redundancy replacements, eliminating the need for separate dedicated redundancy hardware.
2Reliability
If traditional column redundancy schemes process data statically before user access, then defective columns can be replaced, but processing time and latency increase
Solution Approach 1:
The patent transitions from static pre-processing of redundancy data to dynamic on-the-fly replacement during data transfer. The redundancy replacement occurs dynamically as data is being clocked in or out, adapting to the actual data flow rather than requiring complete static processing beforehand.
Solution Approach 2:
The redundancy replacement operation continues concurrently with normal data transfer operations. While user data is being clocked through the serial interface, the same data path continuously performs redundancy replacements without interruption, maximizing utilization of the data path throughout the entire operation.
3Reliability
If redundancy replacement is performed before data-clocking periods, then defective data can be corrected, but latency increases and controller logic remains under-utilized
Solution Approach 1:
The system prepares redundancy data in advance by latching it into registers during idle periods, but the actual replacement action occurs during the data-clocking period when the data path is already active. This preliminary preparation enables the replacement to happen concurrently rather than requiring separate processing time.
Solution Approach 2:
The controller logic remains continuously utilized by performing redundancy replacements during the same time period that user data is being transferred. The data path and control logic that would otherwise be idle or under-utilized are kept busy with redundancy operations, eliminating wasted capacity.
Data Source
AI summary
A dynamic column redundancy replacement system for programming and reading a non-volatile memory system includes an input data replacement logic block and an output data replacement logic block. A column redundancy match logic block compares a user address to latched fuse addresses of bad columns and identifies address matches to facilitate the replacement of bits from defective memory cells with replacement redundancy bits.