True Complement Dynamic Comparator for Low-Power Bit-Line Comparison
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Solution Overview
Problem
Modern data processing systems using dynamic logic circuits face inefficiencies in power consumption and area usage due to the toggling of output nodes with clock phase changes, even when the logical value remains unchanged, and existing comparator circuits are not optimized for complementary dynamic bit lines.
Innovation Solution
A true complement dynamic circuit is designed to efficiently compare binary data using a 1-bit compare circuit with dynamic first and second input signals that are complementary during the evaluation phase, utilizing a bit line pass gate device topology and cross-coupled NAND logical components to implement XNOR or XOR logical behaviors, allowing for flexible comparison operations and reduced logical stages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If dynamic logic circuits are used for Boolean operations, then speed and area consumption are improved, but power consumption increases due to output node toggling with each clock cycle
Solution Approach 1:
The patent applies dynamic logic circuits with clocked operation to achieve fast Boolean operations. The circuit transitions between precharge and evaluation phases dynamically, allowing rapid computation while managing power through phase-based operation rather than continuous switching.
Solution Approach 2:
The patent implements periodic clock cycles with distinct precharge and evaluation phases. During the precharge phase, the output node is reset; during the evaluation phase, the Boolean function is computed. This periodic operation allows the circuit to maintain speed while reducing unnecessary switching activity and associated power consumption.
2Adaptability or versatility
If conventional comparator circuits are used, then comparison functionality is achieved, but area efficiency is reduced and compatibility with complementary dynamic bit lines is poor
Solution Approach 1:
The patent designs a comparator circuit that universally handles both true and complementary dynamic bit lines through the same evaluation logic. The circuit can compare bits in either true or complement form without requiring separate dedicated circuits, improving area efficiency while maintaining full comparison functionality.
Solution Approach 2:
The patent changes the parameter of input signal representation by accepting both true and complementary forms directly in the evaluation phase. This parameter flexibility allows the circuit to work efficiently with complementary dynamic bit lines commonly used in memory systems, eliminating the need for additional decoding logic and reducing area.
Data Source
AI summary
A true complement dynamic circuit for combining, in particular comparing, binary data on dynamic first and second input signals to third and fourth input signals, comprising at least a 1-bit compare circuit, wherein the dynamic first and second input signals are complementary signals during an evaluation phase, wherein a logical behavior is determined by the third and fourth input signals. A method for operating a true complement dynamic circuit for combining, in particular comparing, binary data on dynamic first and second input signals to third and fourth input signals, comprising operating at least a 1-bit compare circuit, wherein the dynamic first and second input signals are complementary signals during an evaluation phase, determining a logical behavior by the third and fourth input signals.