Dynamic Comparator Boost Circuit for Faster ADC Latching
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Solution Overview
Problem
Dynamic comparators in analog-to-digital converters (ADCs) face challenges in latching speed due to semiconductor process variation, low supply voltage, and low temperature, while maintaining power efficiency.
Innovation Solution
A dynamic comparator design incorporating an amplifier circuit, latch circuit, reset circuit, boost circuit, and ready circuit, which includes a boost circuit with supplemental current paths to enhance latching speed and maintain power efficiency by minimizing static current consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a latching stage is added to generate full-scale output voltage, then the comparator provides complete output swing, but the latching speed becomes slow under adverse conditions
Solution Approach 1:
The patent applies preliminary action by pre-charging the latching nodes to a voltage level closer to the final output state before the latching operation begins. This reduces the voltage swing required during latching, thereby improving latching speed under adverse conditions such as low supply voltage and low temperature while still achieving full-scale output voltage.
2Speed
If means are added to improve latching speed, then the comparison function becomes faster, but static current consumption increases
Solution Approach 1:
The patent employs periodic action by using clocked control signals to enable current paths only during the active latching phase. The current consumption occurs periodically during the comparison and latching windows, while remaining zero during other phases. This allows speed improvement during active operation without introducing continuous static current consumption.
Solution Approach 2:
The patent applies discarding and recovering by dynamically enabling and disabling current paths based on operational phase. During the comparison phase, current paths are enabled to provide fast latching; during idle phases, these paths are disabled to eliminate static current consumption. The system recovers the ability to provide high current when needed by re-enabling the paths on the next active phase.
3Use of energy by stationary object
If the comparator operates under low supply voltage, then power efficiency is improved, but latching speed deteriorates
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting the effective voltage swing and current path resistance based on the operational requirements. The pre-charging mechanism changes the initial voltage parameter of the latching nodes, while the clocked current paths change the effective resistance parameter during latching. This allows fast latching to be achieved even under low supply voltage conditions, maintaining both power efficiency and speed.
Data Source
AI summary
A comparator is disclosed. The comparator includes an amplifier circuit, a latch circuit, and a boost circuit. The amplifier is configured to amplify a difference between the first and second differential inputs during an active phase of the comparator. The latch circuit includes first and second transistors, respectively coupled to first and second differential amplifier outputs, and configured to respectively drive first and second legs of the latch circuit during the active phase. The boost circuit includes first and second boost transistors respectively coupled to the first and second differential amplifier outputs, and configured to respectively provide a first supplemental current to the first differential output of the latch circuit and a second supplemental current to the second differential output of the latch circuit.