Dynamic Comparator Branch Topology for Faster Low-Power Comparison
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Solution Overview
Problem
Dynamic comparators, particularly those used in successive approximation analog-to-digital converters, face challenges due to manufacturing dispersions and the 'kick-back effect' which lead to comparison errors and increased power consumption, especially when the stabilization time of the ring structure increases with decreasing voltage intervals.
Innovation Solution
A dynamic comparator design with two branches of alternated logic gates, where each branch is biased by different voltages, allowing edges to propagate at varying speeds, and the order of arrival determines the comparison result, reducing the number of gates required for stabilization and thus decreasing response time and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a dynamic latched comparator is used, then the comparison function is achieved, but manufacturing dispersions cause comparison errors and the kick-back effect reduces accuracy
Solution Approach 1:
The comparator is divided into multiple independent logic gates (first logic gate, second logic gate, third logic gate, fourth logic gate) arranged in a specific configuration. Each gate processes the comparison independently, and the final result is obtained by combining these independent processing results, thereby reducing the impact of manufacturing dispersions on overall accuracy.
Solution Approach 2:
An intermediate node is introduced between the input voltages and the final comparison output. This intermediate node receives the first voltage and second voltage as inputs and generates an intermediate signal that is then processed by the logic gates. This intermediary structure helps to isolate and reduce the kick-back effect from directly impacting the final comparison result.
2Measurement precision
If the number of logic gates in the ring structure is increased to improve stabilization, then comparison accuracy improves, but response time increases and power consumption increases
Solution Approach 1:
Instead of using a large number of logic gates to ensure complete stabilization, the invention uses a minimal sufficient configuration of four logic gates. This partial action approach achieves the necessary comparison accuracy without the excessive response time and power consumption that would result from adding more gates to the ring structure.
3Measurement precision
If the number of logic gates is increased to reduce manufacturing dispersion effects, then comparison accuracy improves, but power consumption increases
Solution Approach 1:
The invention employs exactly four logic gates in a specific configuration, which is the minimal number sufficient to achieve accurate comparison results while minimizing power consumption. Adding more gates would provide diminishing returns in accuracy while significantly increasing power consumption, so this partial action approach optimizes the trade-off.
Solution Approach 2:
The logic gates are biased by different voltages (first voltage and second voltage) to optimize their operating parameters. By carefully selecting and adjusting these bias voltages, the gates operate at optimal points that maximize comparison accuracy while minimizing power consumption, achieving high precision without excessive energy use.
Data Source
AI summary
The present description concerns a comparator (1) of a first voltage (V+) and of a second voltage (V−), comprising first (100) and second (102) branches each comprising a same succession of alternated first (106) and second (108) gates in series between a node (104) and an output (1002; 1022) of the branch (100; 102), wherein: each branch starts with a first gate (106), each gate (106; 108) has a second node (114) receiving a bias voltage, the second node (114) of each first gate (106) of the first branch (100) and of each second gate (108) of the second branch (102) receives the first voltage (V+), the second node of the other gates receiving the second voltage (V−), and an order of arrival of the edges on the outputs (1002; 1022) of the branches determines a result of a comparison.