Two-Stage Dynamic Comparator With Offset Calibration Timing
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Solution Overview
Problem
Existing comparators in Analog to Digital Converters (ADCs) face challenges in achieving low noise, low offset, and high speed due to limitations in transistor saturation time and design complexity, particularly in dynamic comparators with single or two-stage configurations.
Innovation Solution
A two-stage dynamic comparator design with a comparing input unit and a latching unit, utilizing different strobe signals for each stage to extend transistor saturation time and include a calibration unit for offset calibration, allowing for adjustable delay between strobe signals to optimize noise, offset, and power performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If cascading transistors are added from supply voltage to ground to limit overdrive voltage, then the comparator's noise performance is improved, but the period of input transistors operating in saturation region is restricted and speed is degraded
Solution Approach 1:
The comparator is divided into two independent stages: a first comparing stage and a second comparing stage. Each stage has its own strobe signal control, allowing the input transistors to operate in saturation region for extended periods. The first stage processes input signals while the second stage latches the result, separating the functions to maintain both noise performance and speed.
Solution Approach 2:
The patent uses dynamic strobe signals to control the timing of each stage independently. The first strobe signal enables the first comparing unit, and the second strobe signal enables the second comparing unit with an adjustable delay. This dynamic control allows input transistors to remain in saturation region longer, improving speed while maintaining noise performance through proper timing separation.
2Power
If PMOS output-latch stage is used in two stage dynamic comparator, then the driving current at the load is reduced, but the duration for input transistors to operate in saturation region is limited and delay variation increases
Solution Approach 1:
The patent employs dynamic strobe signals to control the timing of each stage independently. The first strobe signal controls the first comparing unit while the second strobe signal controls the second comparing unit with an adjustable delay between them. This allows input transistors to operate in saturation region for extended periods without being limited by the latch stage timing, thereby increasing saturation operation duration and reducing delay variation.
3Measurement precision
If offset calibration with digital control is implemented by inserting unbalance capacitance at comparator outputs, then offset voltage is suppressed, but the speed of the comparator is degraded with extra output loads
Solution Approach 1:
The patent performs offset calibration before the main comparison operation. The calibration unit adjusts offset voltages in advance by controlling the first and second comparing units with calibration signals. This preliminary calibration eliminates the need for extra output load capacitance during normal operation, thereby maintaining high speed while achieving offset suppression.
4Measurement precision
If extra input pair of transistors is added for offset calibration, then offset voltage is suppressed, but design complexity and area are increased by adding extra bias voltage and capacitor
Solution Approach 1:
The patent uses the existing first and second comparing units to perform both normal comparison operations and offset calibration functions. The same comparing input units are reused for calibration by applying calibration signals during a calibration phase, eliminating the need for separate calibration circuitry. This multi-functional approach suppresses offset voltage without increasing design complexity or requiring extra bias voltages and capacitors.
Data Source
AI summary
A comparator is provided and the comparator includes a comparing input unit and a latching unit. Wherein, the comparing input unit has a first input receiving a first comparing signal and has a second input receiving a second comparing signal. The comparing input unit drives a first intermediate node signal at a first intermediate node depending on the first comparing signal according to a first strobe signal, and the comparing input unit drives a second intermediate node signal at a second intermediate node depending on the second comparing signal according to the first strobe signal. The latching unit determines a comparing result according to at least one of the first intermediate node signal and the second intermediate node signal. In addition, the latching unit latches the comparing result according to a second strobe signal.