Dynamic Comparator Circuit With Common-Mode Stabilization
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Solution Overview
Problem
Conventional high-speed ADCs face limitations in speed due to increased regeneration time constant and common mode instability, which leads to higher bit error rates and power consumption.
Innovation Solution
A high-speed comparator design with smaller PMOS transistors and series inverters, coupled with auxiliary cross-coupled NMOS transistors to reduce capacitance and eliminate common mode instability, improving regeneration time constant without increasing power dissipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional high-speed ADC design is used, then speed is improved, but regeneration time constant increases and common mode instability occurs
Solution Approach 1:
An auxiliary cross-coupled NMOS transistor pair is introduced as an intermediary element to counteract the common mode instability caused by the series inverters. The auxiliary transistors act as a mediator that provides negative feedback to stabilize the common mode voltage, thereby resolving the contradiction between speed improvement and common mode stability.
Solution Approach 2:
The patent changes the transistor sizing parameters, specifically using smaller PMOS transistors in the series inverters compared to conventional designs. This parameter change reduces the capacitance at the regeneration node, thereby reducing the regeneration time constant and improving speed while the auxiliary NMOS transistors compensate for the resulting common mode instability.
2Loss of time
If series inverters with smaller PMOS transistors are used, then regeneration time constant is reduced, but common mode instability increases
Solution Approach 1:
The auxiliary cross-coupled NMOS transistor pair functions as a counterweight to the destabilizing effect of the series inverters. By sizing the auxiliary NMOS transistors appropriately, their stabilizing influence counterbalances the common mode instability introduced by the smaller PMOS transistors in the series inverters, allowing the system to achieve both reduced regeneration time constant and maintained common mode stability.
3Reliability
If conventional PMOS transistor sizing is used, then common mode stability is maintained, but regeneration time constant increases and speed decreases
Solution Approach 1:
The comparator circuit is segmented into functional blocks: the main regeneration path with series inverters and smaller PMOS transistors for speed, and a separate auxiliary cross-coupled NMOS transistor pair for stability. This segmentation allows each block to be optimized independently - the series inverters provide fast regeneration while the auxiliary transistors provide common mode stability without interfering with the speed optimization.
Data Source
AI summary
A comparator includes a differential input pair of transistors, a pair of cross coupled n-channel metal-oxide-semiconductor field-effect (NMOS) transistors, a pair of p-channel metal-oxide semiconductor field-effect (PMOS) transistors, a first inverter, and a second inverter. The differential input pair of transistors includes a first input transistor and a second input transistor. The pair of cross coupled NMOS transistors includes a first NMOS transistor and a second NMOS transistor. The pair of PMOS transistors includes a first PMOS transistor and a second PMOS transistor. The pair of PMOS transistors are coupled to the pair of cross coupled NMOS transistors. The first inverter is coupled in series with the first PMOS transistor. The second inverter is coupled in series with the second PMOS transistor.