Dynamic Comparator Equalization for Fast Low-Power Switching
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Solution Overview
Problem
Existing dynamic comparators face challenges in achieving high-speed operation with low power consumption without DC power consumption and compromising accuracy, particularly due to sensitivity to input common-mode variations and the need for static equalization which increases power usage.
Innovation Solution
A dynamic comparator with an integrated dynamic transconductance circuit that equalizes bias voltages in the reset mode, eliminating the need for additional DC power and allowing for faster transition to comparison mode by converting voltage to current, thereby reducing recovery time and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a static equalization circuit is added to enhance operating speed, then the operating speed is improved, but the DC power consumption increases
Solution Approach 1:
The patent applies dynamic equalization by switching the equalization circuit on/off based on operational phase. During reset phase, the equalization circuit is enabled to balance output voltages. During comparison phase, it is disabled to eliminate static power consumption. This dynamic switching resolves the contradiction between speed enhancement and power consumption.
Solution Approach 2:
The equalization circuit operates periodically - activated during reset phase and deactivated during comparison phase. This periodic operation allows the system to benefit from equalization when needed while avoiding continuous power consumption, thus improving operating speed without incurring constant DC power overhead.
2Speed
If the recovery time of output common-mode voltage is reduced for faster operation, then the operating speed is improved, but the accuracy may be compromised
Solution Approach 1:
The equalization circuit performs preliminary action by pre-balancing the output voltages during the reset phase before the comparison phase begins. This preliminary equalization ensures that both output nodes start from a balanced state, reducing the recovery time needed during comparison while maintaining accuracy through proper initial conditions.
Solution Approach 2:
The patent replaces traditional static equalization mechanisms with a dynamic switching approach. By using clock-controlled switches to enable equalization only during reset phase, the system achieves faster recovery without compromising accuracy, as the equalization is precisely timed and controlled rather than continuously active.
3Difficulty of detecting and measuring
If the transistor stack height is increased to improve input impedance, then the input impedance is improved, but the supply voltage range is limited
Solution Approach 1:
The patent segments the comparator into multiple functional blocks: preamplifier, equalization circuit, and switched latch. This segmentation allows the input stage to achieve high impedance through proper transistor configuration while the supply voltage constraint is addressed by distributing functionality across segments, enabling independent optimization of each block.
Solution Approach 2:
The patent applies local quality by optimizing transistor characteristics in specific regions. The input transistors are configured for high impedance, while the equalization and latch circuits are designed with voltage headroom considerations. This localized optimization allows high input impedance without uniformly limiting the supply voltage across the entire circuit.
4Measurement precision
If the tail current is optimized for accuracy, then the accuracy is improved, but the operating speed is reduced
Solution Approach 1:
The patent uses dynamic tail current control where the tail current is optimized for accuracy during the comparison phase but can be adjusted or disabled during the reset phase. This dynamic control allows the system to achieve high accuracy when comparing signals while maintaining fast operation during phase transitions and reset, resolving the speed-accuracy tradeoff.
Solution Approach 2:
The tail current operates periodically - optimized for accuracy during comparison phase and adjusted during reset phase. This periodic optimization allows the circuit to achieve high measurement precision when needed while maintaining fast operating speed during transitions, eliminating the need for a constant compromise between speed and accuracy.
Data Source
AI summary
The present disclosure provides a dynamic comparator with equalization function including a preamplifier, switched latch and dynamic transconductance circuit. The preamplifier amplifies input signals of the dynamic comparator. The dynamic transconductance circuit is inserted between the preamplifier and the switched latch for operating in a reset mode or a comparison mode. When operating in the reset mode, the dynamic transconductance circuit in conjunction with the switched latch performs voltage equalization of output signals of the switched latch, or when operating in the comparison mode, the dynamic transconductance circuit in conjunction with the switched latch receives the output signals generated by the preamplifier and carries out signal transconductance. The switched latch generates output signals as a comparison result of the dynamic comparator based on the transconductance signals generated by the dynamic transconductance circuit. The present disclosure provides a dynamic comparator that reduces the power consumption and increasing the operating speed.