Dynamic Comparator Reset Circuit for High-Speed A/D Precision
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional A/D converters face challenges in maintaining comparison precision when the frequency of the clock signal and analog input signal are high, leading to deterioration in comparator performance and A/D conversion accuracy.
Innovation Solution
A dynamic-type comparator is designed with an input transistor section, a positive feedback section, and a reset section, where the reset section includes a replica circuit to generate a reset voltage, forcibly resetting nodes Vb and Va to a common voltage before comparison, thereby eliminating offset and improving precision.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the frequency of the clock signal and analog input signal are increased to achieve high-speed A/D conversion, then the conversion speed is improved, but the comparison precision deteriorates due to offset and charge remaining at nodes
Solution Approach 1:
The patent applies preliminary action by resetting the nodes Va and Vb to a common voltage level before the comparison operation begins. The reset section includes reset transistors that are activated prior to comparison to discharge any remaining charge at the nodes, ensuring that the comparison starts from a known zero state. This preliminary reset action eliminates offset errors that would otherwise accumulate and degrade precision at high frequencies.
Solution Approach 2:
The patent implements feedback through a replica circuit that mirrors the input transistor section and positive feedback section. The replica circuit generates a reset voltage that is fed back to the reset section, creating a self-regulating mechanism. This feedback loop ensures that the reset voltage is dynamically adjusted based on the actual state of the comparator nodes, maintaining precision even as operating conditions change with frequency.
2Device complexity
If a dynamic-type comparator is used to reduce circuit complexity and power consumption, then device complexity and energy use are reduced, but offset error increases due to charge remaining at nodes
Solution Approach 1:
The patent extracts the offset error problem by separating the reset function from the comparison function. The reset section is designed as a distinct circuit block with reset transistors that operate independently from the input and positive feedback sections. This extraction allows the dynamic-type comparator to maintain its simplicity while adding a dedicated mechanism to remove offset errors by discharging node charges before each comparison cycle.
Solution Approach 2:
The patent introduces an intermediary reset voltage generated by the replica circuit that mediates between the dynamic comparator's simplicity and the need for precision. This reset voltage acts as an intermediary signal that temporarily overrides the dynamic operation to establish a known zero state, then allows the dynamic comparison to proceed without offset interference.
3Measurement precision
If the number of differential amplifiers and comparators is increased to improve resolution, then A/D conversion resolution is improved, but power consumption and occupied area increase
Solution Approach 1:
The patent changes the operational parameters of the comparator by implementing a dynamic type design with clocked operation. Instead of using static high-resolution comparators that consume continuous power, the dynamic design uses clock signals to control the timing of comparison operations. The reset section resets nodes at specific clock phases, allowing the same hardware to achieve high resolution through precise timing control rather than through increased component count.
Data Source
AI summary
A comparator used in a parallel-type A/D converter, wherein a comparator 100 includes reset transistors mra and mrb. When the comparator 100 is in the Reset state, the inverted signal /CLK of the clock signal is given to the PMOS reset transistors mra and mrb so as to forcibly reset both of the voltages at two internal nodes Va and Vb being a differential pair to a predetermined reset voltage by the reset transistors mra and mrb. The inverted signal /CLK of the clock signal is produced with a predetermined delay. Thus, when the comparator 100 is in the Reset state, the point in time at which to cancel the reset of the internal nodes Va and Vb is delayed from that at which the comparator performs a comparison operation. Therefore, even if the frequency of the clock signal and the frequency of the analog input signal are high, the voltages at the internal nodes forming a differential pair are well-balanced when the comparator is in the Reset state, thus improving the voltage comparison precision.