Dynamic Comparator Ring Gates for Faster Stabilization

Solution Overview

Problem

Dynamic comparators, particularly edge pursuit dynamic comparators, face challenges with increased stabilization time and consumption due to the gap between compared voltages, leading to inefficiencies in successive-approximation analog-digital converters.

Innovation Solution

A dynamic comparator design featuring a ring of logic gates with controllable gates that block the propagation of the slowest edge, reducing stabilization time and consumption by optimizing gate polarization and configuration, including MOS transistors for isolating outputs and implementing inverting functions conditioned by synchronization signals.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If edge pursuit dynamic comparator structure is used, then comparison accuracy is improved, but stabilization time increases

Engineering Contradiction:

Improvecomparison accuracyVSAvoidstabilization time

Core Design Contradiction:

Measurement precisionVSLoss of time

Solution Approach 1:

The patent applies dynamics by making the comparator structure adjustable through controllable gates that can be enabled or disabled based on operating conditions. The gate polarization can be dynamically changed to optimize performance for different voltage gap scenarios, allowing the system to adapt between speed-optimized and accuracy-optimized configurations.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The patent changes parameters by adjusting the polarization voltage of controllable gates within the logic gate ring. By varying the polarization parameter, the comparator can optimize its operation for different input voltage differences, thereby reducing stabilization time while maintaining comparison accuracy under varying conditions.

Inventive Principle:

Principle #35Parameter changes

2Measurement precision

If edge pursuit dynamic comparator structure is used, then comparison accuracy is improved, but energy consumption increases

Engineering Contradiction:

Improvecomparison accuracyVSAvoidenergy consumption

Core Design Contradiction:

Measurement precisionVSUse of energy by stationary object

Solution Approach 1:

The patent applies dynamics by making the comparator structure adjustable through controllable gates that can be enabled or disabled based on operating conditions. The gate polarization can be dynamically changed to optimize performance for different voltage gap scenarios, allowing the system to adapt between speed-optimized and accuracy-optimized configurations.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The patent changes parameters by adjusting the polarization voltage of controllable gates within the logic gate ring. By varying the polarization parameter, the comparator can optimize its operation for different input voltage differences, thereby reducing stabilization time while maintaining comparison accuracy under varying conditions.

Inventive Principle:

Principle #35Parameter changes

3Loss of time

If controllable gates are added to block slow edges, then stabilization time is reduced, but device complexity increases

Engineering Contradiction:

Improvestabilization timeVSAvoiddevice complexity

Core Design Contradiction:

Loss of timeVSDevice complexity

Solution Approach 1:

The patent merges the edge-blocking function with the existing logic gate structure by integrating controllable gates into the ring. These controllable gates combine the functions of signal propagation and edge speed control in a single structural element, reducing the need for separate components and minimizing overall device complexity.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The controllable gates serve multiple functions: they act as regular logic gates for signal propagation and simultaneously function as speed-control elements for blocking slow edges. This multi-functionality reduces the need for additional dedicated components, thereby limiting the increase in device complexity while achieving stabilization time reduction.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS11545992B2Dynamic comparator

Publication Date: 2023.01.03 COMMISSARIAT A LENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

AI summary

The present description relates to a comparator (2) comprising a ring of gates (110A, 110B, 110A′, 110B′, 106, 108) in series, wherein: each gate implements an inverting function between a first input (100) and an output (102) of the gate; at least one (110A′, 110B′) gate is controllable and is associated with another gate; each controllable gate (110A′, 110B′) comprises a control input (116) coupled with the output (102) of said associated gate, and prevents switching of its output (102) to a high state if its control input (116) is in the high state, and to a low state otherwise; and the control input (116) of each controllable gate (110A′, 110B′) receives the output (102) of said associated gate if an even number of gates separates these two gates, and receives the complement of said output if not.