Dynamic Comparator Circuit for Low-Noise SAR ADC Conversion
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Solution Overview
Problem
Comparators in successive approximation register digital-to-analog converters (SAR ADCs) face challenges with thermal noise degrading signal-to-noise ratio and kickback noise introducing non-linearity, requiring trade-offs between conversion speed and noise levels.
Innovation Solution
The comparator circuit design includes specific configurations of transistors and control signals to reduce thermal noise by accelerating the regeneration phase without affecting initial integration time, and incorporates cascode transistors to minimize kickback noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If dynamic comparator is used to increase conversion speed, then productivity is improved, but thermal noise increases degrading signal-to-noise ratio
Solution Approach 1:
The comparator operation is divided into distinct phases: an integration phase where inputs are accumulated over a fixed time period, and a separate regeneration phase that is accelerated. This segmentation allows the integration time to remain long enough for low noise, while the regeneration phase can be fast for high speed conversion.
Solution Approach 2:
The integration phase performs the useful work of accumulating input signals before the regeneration phase begins. By completing the integration beforehand with sufficient time duration, the noise is minimized while the subsequent regeneration can proceed rapidly to meet speed requirements.
2Productivity
If dynamic comparator is used to increase conversion speed, then productivity is improved, but kickback noise increases introducing non-linearity
Solution Approach 1:
Cascode transistors are introduced as intermediary elements between the main comparator transistors and the output nodes. These cascode devices act as buffers that isolate the rapid switching actions from the input nodes, preventing kickback noise from propagating back to the inputs while still allowing fast regeneration at the outputs.
3Measurement precision
If pre-amplifier is added to boost input signal level, then measurement precision is improved, but use of energy increases regardless of throughput
Solution Approach 1:
The signal boosting function is performed periodically during the integration phase rather than continuously. The comparator utilizes the natural accumulation of signal voltage during the integration period, providing gain only when needed for the conversion process, thereby eliminating continuous power consumption associated with traditional pre-amplifiers.
Solution Approach 2:
The comparator circuit itself performs the signal boosting function during integration without requiring a separate dedicated pre-amplifier stage. The integration process naturally accumulates and amplifies the input signal voltage, allowing the main comparator transistors to provide both comparison and signal enhancement functions.
Data Source
AI summary
A comparator circuit includes a first transistor configured to receive a first input and a second transistor configured to receive a second input. The comparator circuit further includes a third transistor coupled to a terminal of each of the first and second transistors. The third transistor is configured to be controlled by a first control signal. A gate of a fifth transistor is coupled to a terminal of a fourth transistor at a first node and a gate of the fourth transistor is coupled to a terminal of the fifth transistor at a second node. A sixth transistor is coupled between the first and fourth transistors. A seventh transistor is coupled between the second and fifth transistors. A gate of the sixth transistor and a gate of the seventh transistor are coupled together at a fixed voltage level.