Dynamic Control Voltage Adjustment for Non-Volatile Memory Programming
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Solution Overview
Problem
Current non-volatile memory devices face challenges in improving data input/output speed, particularly during programming operations, due to limitations in controlling voltage levels and program pulses, which can lead to increased error rates and reduced efficiency.
Innovation Solution
The implementation of a memory device with a control system that dynamically adjusts the level of a first control voltage based on temperature and the number of program pulses, utilizing multiple program modes to optimize the programming process, including Incremental Step Pulse Programming (ISPP), to reduce error rates and enhance data programming speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of program pulses is increased to improve data programming speed, then productivity is improved, but the error rate increases due to voltage degradation
Solution Approach 1:
The patent implements dynamic adjustment of control voltage levels based on the number of program pulses applied. The control voltage is adjusted in different program modes (first, second, third modes) depending on the pulse count, allowing the system to adapt to voltage degradation while maintaining programming speed. This dynamic adjustment resolves the contradiction by making the voltage parameter variable rather than fixed.
Solution Approach 2:
The patent changes the control voltage parameter dynamically during the programming process. By modifying the control voltage level based on the number of program pulses and the selected program mode, the system maintains optimal programming conditions even after multiple pulses, thereby reducing error rates while preserving programming speed.
2Reliability
If the control voltage level is increased to reduce error rates, then reliability is improved, but the data programming speed decreases
Solution Approach 1:
The system dynamically adjusts the control voltage level based on the programming stage and selected mode. In early programming stages or faster modes, lower voltages are used to maintain speed, while in later stages or when error rates increase, voltages are adjusted to maintain reliability. This dynamic approach resolves the contradiction by applying different voltage levels at different times rather than using a consistently high voltage.
Solution Approach 2:
The patent employs periodic verification operations between program pulses to monitor programming status and adjust subsequent voltage levels accordingly. This periodic feedback mechanism allows the system to maintain lower voltages when programming is proceeding well (maintaining speed) while increasing voltages when verification indicates potential errors (maintaining reliability).
3Adaptability or versatility
If multiple program modes are implemented to optimize programming, then adaptability is improved, but device complexity increases
Solution Approach 1:
The patent segments the programming process into distinct program modes (first, second, third modes) and verification operations. Each mode corresponds to different control voltage levels and programming conditions. This segmentation allows the complex programming process to be divided into manageable, selectable segments, making the complexity organized and controllable rather than chaotic.
Solution Approach 2:
The system uses verification operations that provide feedback on the programming status to determine which program mode to apply next. This feedback mechanism allows the control system to automatically select appropriate program modes based on actual programming progress, reducing the need for complex manual control while maintaining adaptability across different programming scenarios.
Data Source
AI summary
A memory device includes a controller that performs a program verification after a first program pulse is applied to the at least one non-volatile memory cell. The first program pulse is applied during a data program operation and the data program operation includes applying program pulses to program multi-bit data to the at least one non-volatile memory cell. The controller also determines a program mode for the at least one non-volatile memory cell based on a result of the program verification, and changes at least one of a level of a first control voltage based on the program mode. The first control voltage is applied to a drain select line coupled to the at least one non-volatile memory cell.