Dynamic Core Allocation in Memory Access Devices

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Solution Overview

Problem

In multifunction direct memory access (MDMA) controllers, programming engines often remain idle when cores are not performing calculations, leading to resource wastage due to a 1:1 core-to-engine ratio, where each core is designed to have a corresponding programming engine.

Innovation Solution

A memory access device with a command manager and a slot management unit that allocates cores to programming engines dynamically, using bitmaps to identify pending and executing commands, allowing for efficient allocation and deallocation of cores to programming engines, even when their number is less than the number of cores, thereby minimizing idle time.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a 1:1 core-to-programming engine ratio is used, then each core has a dedicated programming engine, but programming engines remain idle when cores are not performing calculations, leading to resource wastage

Engineering Contradiction:
Improvededicated programming engine availabilityVSAvoidresource wastage
Core Design Contradiction:
ReliabilityVSLoss of energy

Solution Approach 1:

The patent implements a many-to-one mapping where multiple cores share a single programming engine. The slot management unit dynamically allocates and deallocates programming engines to different cores based on command queues and execution status, allowing one programming engine to serve multiple cores sequentially rather than requiring dedicated engines for each core.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Quantity of substance

If the number of programming engines is reduced to less than the number of cores, then hardware resources are conserved, but idle time of programming engines increases without dynamic allocation

Engineering Contradiction:
Improvenumber of programming enginesVSAvoididle time of programming engines
Core Design Contradiction:
Quantity of substanceVSLoss of time

Solution Approach 1:

The patent introduces dynamic allocation mechanisms including a slot management unit that monitors command queues and programming engine status in real-time. The system uses bitmaps to track core-programming engine mappings and dynamically reassigns engines to waiting cores, transforming the static resource allocation into a dynamic system that adapts to changing workloads and minimizes idle time.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent ensures continuous utilization of programming engines by implementing a command queue system and round-robin arbitration. When one core's commands are being executed, the slot management unit identifies and assigns the programming engine to another core with pending commands, ensuring the engine remains continuously productive without idle gaps.

Inventive Principle:
Principle #20Continuity of useful action

3Productivity

If dynamic allocation of cores to programming engines is implemented, then resource utilization is maximized, but system complexity increases due to allocation management

Engineering Contradiction:
Improveresource utilizationVSAvoidallocation management complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The slot management unit autonomously monitors command queues, identifies available programming engines, and performs allocations without external intervention. The system self-manages the complexity of dynamic allocation through automated bitmap tracking and round-robin arbitration, eliminating the need for complex external scheduling mechanisms while maximizing resource utilization.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS20250013501A1Allocating cores to empty programming engines using a memory access device
Publication Date: 2025.01.09 XCENA INC
  • US20250013501A1 patent drawing
  • US20250013501A1 patent drawing
  • US20250013501A1 patent drawing

AI summary

As one aspect of the present disclosure, a memory access device is disclosed. The device comprises: a command manager configured to receive and manage one or more commands from a plurality of cores; a programming engine unit comprising one or more programming engines configured to perform calculations in response to the one or more commands; and a direct memory access (DMA) controller configured to perform at least one of read access and write access to a memory external to the memory access device in response to the one or more commands, wherein the command manager comprises a command memory configured to store the one or more commands, and a slot management unit configured to allocate one or more cores that correspond to the one or more commands, respectively, to the one or more programming engines in sequence.