Dynamic Core Selection for Memory Subsystem Latency
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Solution Overview
Problem
In memory sub-systems, not all cores are equally utilized at all times, leading to idle processing resources while other cores have a backlog of operations, resulting in inefficiencies and potential latency issues.
Innovation Solution
The memory sub-system dynamically selects a processing core to handle the second portion of an access operation, allowing different cores to process different portions of the same operation, such as using a read core for incoming read commands and a write core for processing read responses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a single core processes both incoming commands and outgoing responses, then the core structure is simple, but processing resources remain idle while other cores have backlogs, reducing overall efficiency
Solution Approach 1:
The patent segments the processing of access operations into two distinct portions: command processing and response processing. Different cores are assigned to handle these separate portions, allowing parallel processing and preventing idle resources. This segmentation resolves the contradiction by dividing the monolithic processing task into manageable parts that can be executed concurrently by different cores.
Solution Approach 2:
The patent implements dynamic core selection where the system can adaptively choose which core processes responses based on current workload conditions. This dynamic approach allows the system to optimize processing efficiency in real-time while managing core allocation complexity through flexible, condition-based decision-making rather than static assignments.
2Speed
If multiple cores are used for parallel processing, then processing speed increases, but resource imbalance occurs where some cores are idle while others have backlogs
Solution Approach 1:
The patent ensures continuous useful action by keeping multiple cores actively engaged in processing different portions of access operations simultaneously. By assigning command processing to one core and response processing to another, the system eliminates idle periods and maintains continuous productive work across all cores, resolving the resource imbalance while preserving parallel processing speed advantages.
3Loss of time
If the same core handles both command reception and response transmission, then coordination is simple, but latency increases due to sequential processing
Solution Approach 1:
The patent segments the access operation into distinct command and response portions handled by different cores. This segmentation enables parallel execution of command processing and response transmission, significantly reducing processing latency. The added coordination complexity is managed through structured inter-core communication protocols that track operation states and facilitate smooth handoff between cores.
Solution Approach 2:
The patent introduces intermediary mechanisms such as status registers and control signals that facilitate coordination between cores handling different portions of access operations. These intermediaries enable efficient information exchange and synchronization without creating bottlenecks, resolving the latency issue while managing coordination complexity through standardized communication interfaces.
Data Source
AI summary
Methods, systems, and devices for the dynamic selection of cores for processing responses are described. A memory sub-system can receive, from a host system, a read command to retrieve data. The memory sub-system can include a first core and a second core. The first core can process the read command based on receiving the read command. The first core can identify the second core for processing a read response associated with the read command. The first core can issue an internal command to retrieve the data from a memory device of the memory sub-system. The internal command can include an indication of the second core selected to process the read response.