Dynamic Core Voltage Adjustment via Ring Oscillator Feedback
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Solution Overview
Problem
Digital circuits consume excessive power due to high quiescent states and increased power consumption with temperature, exacerbated by decreasing feature sizes and subtle core voltage swings, leading to inefficiencies and heat generation.
Innovation Solution
An integrated circuit system that dynamically adjusts core voltage based on a ring oscillator's delay compared to an external clock signal, ensuring the oscillator delay remains within a predefined margin, allowing for a lower core voltage setting without compromising speed, thereby reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the core voltage is set higher to ensure adequate speed across wide temperature conditions, then the speed reliability is improved, but the power consumption increases
Solution Approach 1:
The patent implements dynamic voltage scaling by continuously monitoring the ring oscillator frequency and adjusting the core voltage in real-time. The voltage control logic modifies the core voltage based on actual operating conditions rather than using a fixed conservative voltage setting, allowing the system to operate at lower voltages when conditions permit while maintaining speed requirements.
Solution Approach 2:
The patent changes the voltage parameter dynamically based on temperature and oscillator frequency measurements. By using the ring oscillator as a temperature-sensitive reference and adjusting voltage accordingly, the system adapts the electrical parameter (voltage) to match actual operating conditions, reducing power consumption while maintaining reliability.
2Use of energy by moving object
If the core voltage is set lower to reduce power consumption, then the power efficiency is improved, but the speed may become insufficient under varying temperature conditions
Solution Approach 1:
The patent employs feedback control by continuously monitoring the ring oscillator frequency and using this information to adjust the core voltage. The voltage control logic receives feedback about actual circuit performance and modifies the voltage setting accordingly, ensuring speed requirements are met while maximizing power efficiency. The feedback loop compares actual oscillator frequency against target frequencies and adjusts voltage to maintain optimal operation.
Solution Approach 2:
The system uses the ring oscillator's inherent temperature sensitivity to automatically detect operating conditions and trigger appropriate voltage adjustments without external intervention. The oscillator effectively serves as a self-diagnostic element that informs the voltage control logic about actual circuit performance, enabling the system to self-regulate its voltage setting based on real-time conditions.
3Reliability
If a larger margin of error is used in core voltage selection to ensure speed across all conditions, then the speed reliability is improved, but the power consumption increases due to higher voltage setting
Solution Approach 1:
The patent replaces the static conservative voltage margin with a dynamic adjustment mechanism. Instead of always operating with a large fixed voltage margin to ensure speed reliability, the system dynamically adjusts the voltage based on actual ring oscillator frequency measurements, maintaining only the necessary margin at any given moment. This eliminates the continuous energy loss associated with unnecessarily high voltage settings.
Solution Approach 2:
The patent changes the voltage parameter from a fixed conservative value to a dynamically adjusted value based on actual operating conditions. By using temperature-compensated frequency measurements from the ring oscillator as the basis for voltage setting, the system optimizes the voltage parameter to match actual needs rather than worst-case assumptions, reducing energy loss while maintaining reliability.
Data Source
AI summary
A system for adjusting core voltage of an integrated circuit to optimize power savings has a ring oscillator on the integrated circuit for providing a ring oscillator signal. The system also has compare logic on the integrated circuit configured to compare the ring oscillator signal with a clock signal from a clock external to the integrated circuit. The compare logic is configured to make a determination whether a frequency of the clock signal is within a predefined margin of a frequency of the ring oscillator and to adjust the core voltage of the integrated circuit based on the determination. Through such adjustments, the core voltage is lowered while ensuring that the core voltage does not reach a point that causes timing errors.