Dynamic CPU Interrupt Intervals for USB Power Management

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Solution Overview

Problem

The existing power-saving mechanisms in computer systems are inefficient due to redundant CPU awakenings caused by USB host controllers restoring from idle states at fixed timing intervals, which disrupt the CPU's power-saving state and limit overall power-saving effectiveness.

Innovation Solution

A method and device that adjust power-saving strategies by using a power management controller to detect the CPU's state and interrupt it at varying intervals based on its power state, allowing shorter intervals during high power states and longer intervals during low power states to optimize CPU rest periods and USB device performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the USB host controller restores from idle state at fixed timing intervals, then the USB device can check for updated descriptor data, but the CPU is redundantly awakened and cannot maintain power-saving state

Engineering Contradiction:
ImproveUSB device operation reliabilityVSAvoidCPU power consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The USB host controller proactively sends an interrupt signal to the CPU before the CPU needs to be awakened for other reasons. By anticipating the CPU's need to wake up and sending the interrupt in advance, the system allows the CPU to enter deeper idle states knowing it will be awakened when necessary, thereby reducing overall power consumption while maintaining USB operation reliability.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system implements a feedback mechanism where the USB host controller monitors system state and dynamically adjusts its interrupt timing based on CPU activity. When the CPU is determined to be in a working state, the controller adjusts interrupt intervals to avoid redundant awakenings, creating a closed-loop control system that optimizes power savings while maintaining operational reliability.

Inventive Principle:
Principle #23Feedback

2Productivity

If the CPU is interrupted at short intervals during power-saving mode, then USB device performance is maintained, but power-saving effectiveness is reduced

Engineering Contradiction:
ImproveUSB device performanceVSAvoidSystem power consumption
Core Design Contradiction:
ProductivityVSLoss of energy

Solution Approach 1:

The interrupt interval is made dynamic rather than fixed. The USB host controller adjusts the interrupt interval based on real-time assessment of CPU working state. When the CPU is busy with other tasks, shorter interrupt intervals are used to maintain USB performance. When the CPU is idle, longer intervals are used to maximize power savings. This dynamic adjustment resolves the contradiction between maintaining performance and reducing energy loss.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system changes the parameter of interrupt interval based on CPU state. By monitoring whether the CPU is in a working state or idle state, the USB host controller modifies the interrupt interval parameter accordingly - using shorter intervals when CPU is working and longer intervals when CPU is idle. This parameter adaptation allows the system to optimize both USB performance and power consumption under different operating conditions.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS8281171B2Adjustment of power-saving strategy depending on working state of CPU
Publication Date: 2012.10.02 VIA TECH INC
  • US8281171B2 patent drawing
  • US8281171B2 patent drawing
  • US8281171B2 patent drawing

AI summary

In a method for adjusting power-saving strategy of a peripheral device controller in communication with a CPU, whether the CPU is in a working state while the peripheral device enters a power-saving mode is first determined. Then, interrupt the CPU at relatively short intervals during the power-saving mode if the CPU is in the working state; and interrupt the CPU at relatively long intervals during the power-saving mode if the CPU is not in the working state.