Dynamic CRC and Voltage Scaling in Memory Subsystems
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Solution Overview
Problem
Enabling cyclic redundancy check (CRC) in DRAM systems to mitigate noise on data pins results in significant bandwidth loss, compromising performance while providing noise-immunity.
Innovation Solution
Implementing a dynamic system that enables or disables CRC and adjusts the voltage level of the VDDQ_SOC power supply rail based on the throughput or speed of the DDR link, as well as the type of operations (read or write) being performed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If CRC is enabled to mitigate noise on data pins, then noise-immunity is improved, but bandwidth is significantly reduced
Solution Approach 1:
The patent implements dynamic CRC enablement where the CRC function is selectively activated or deactivated based on real-time noise conditions detected through error monitoring. This allows the system to adapt between reliability-oriented mode (CRC enabled) and performance-oriented mode (CRC disabled), resolving the contradiction by making the CRC status dynamic rather than fixed.
Solution Approach 2:
The patent changes the operational parameter of CRC enablement status based on detected error rates and noise conditions. When error rates exceed thresholds, CRC is enabled to improve reliability; when error rates are acceptable, CRC is disabled to maintain maximum bandwidth, thus dynamically adjusting the parameter to balance reliability and productivity.
2Reliability
If fixed high voltage is supplied to PHY to meet signal integrity specifications, then signal integrity is improved, but power consumption increases
Solution Approach 1:
The patent implements dynamic voltage scaling where the PHY voltage is adjusted in real-time based on operational mode (read/write), data rate, and signal quality conditions. During read operations, voltage is reduced to save power while maintaining sufficient signal integrity. During write operations or high-noise conditions, voltage is increased to ensure signal integrity, thus dynamically balancing reliability and energy consumption.
Solution Approach 2:
The patent changes the voltage parameter supplied to the PHY based on operational requirements and detected signal quality. The system monitors error rates and adjusts voltage levels accordingly - lowering voltage during low-stress operations to reduce power consumption while maintaining signal integrity thresholds, and increasing voltage when signal integrity is compromised.
3Reliability
If high voltage is supplied to meet write operation requirements, then write reliability is improved, but power is wasted during read operations
Solution Approach 1:
The patent implements operation-specific voltage scaling where the PHY voltage is dynamically adjusted based on whether the current operation is a read or write. During write operations, high voltage is supplied to ensure reliable data transmission. During read operations, voltage is reduced to minimum necessary levels, eliminating wasted power while maintaining sufficient signal integrity for read operations.
Data Source
AI summary
Hardware and/or software that dynamically enables or disables CRC and/or adjust voltage level of power supply to a physical layer block on a host by determining an optimum tradeoff between power and performance. The hardware and/or software decreases the voltage level for the power supply and enables CRC to compensate signal errors (e.g., errors from signal integrity issues). Hardware and/or software dynamically adjusts voltage level of the power supply rail based on the throughput or speed of the DDR link. In some examples, depending on read or write operations, the voltage level of the power supply rail is adjusted.