Dynamic Current Limit Circuit for Buck Converters
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Solution Overview
Problem
Existing Buck switching converter designs fail to provide well-controlled minimum and maximum current limits, especially in pulse-frequency modulation (PFM) and pulse-width modulation (PWM) modes, leading to inefficiencies and inability to support a range of currents.
Innovation Solution
A dynamic current limit circuit is introduced, utilizing a sync current output with a first Digital to Analog Converter (IDAC) and a dynamic sleep amplifier, along with mirror circuits to accurately set and scale current limits, ensuring they match PFM and PWM limits, and adjust based on the number of active phases.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If an amplifier is used to increase the current reference in existing Buck switching converter designs, then the current limit can be adjusted, but the minimum current limit value cannot be well-controlled and may not be smaller than the normal PFM mode current limit
Solution Approach 1:
The patent implements a dynamic current limit circuit that transitions between different current limit modes (PFM and PWM) based on operating conditions. The circuit dynamically adjusts the current limit reference by selecting between a PFM current limit path and a PWM current limit path, ensuring the minimum current limit is well-controlled and smaller than normal PFM mode current limit, thereby resolving the contradiction between adaptability and measurement precision.
2Adaptability or versatility
If existing circuit implementations are used to control the maximum current limit value, then some control is achieved, but the maximum value does not track the accurately controlled PWM current limit
Solution Approach 1:
The patent employs a feedback mechanism where the PWM current limit serves as a reference that the dynamic current limit circuit tracks. The circuit monitors the PWM current limit signal and adjusts its output to match this reference, ensuring the maximum current limit value accurately tracks the PWM current limit. This feedback approach resolves the contradiction between adaptability and measurement precision for maximum current limit control.
3Loss of energy
If PFM mode is used for low load currents with a low current limit to maximize efficiency, then efficiency is improved, but the converter cannot support a range of currents when the minimum current limit is not smaller than the normal PFM mode current limit
Solution Approach 1:
The patent creates a dynamic current limit circuit that can operate in two distinct modes: PFM mode for low load currents with a controlled minimum current limit smaller than normal PFM mode limit, and PWM mode for higher currents. The circuit dynamically switches between these modes based on the load conditions, ensuring both high efficiency at low loads (by maintaining appropriate current limits) and broad current support range (by enabling PWM mode when needed), thereby resolving the contradiction between energy loss and adaptability.
Data Source
AI summary
A system is disclosed which provides a dynamic current limit circuit that accurately defines both the lower and the upper limits for the current limit. The circuit ensures both the lower and upper current limits are well-controlled. The lower current limit is matched to the normal pulse-frequency modulation (PFM) limit, and the upper current limit is matched to the pulse-width modulation (PWM) limit. This implementation has several key benefits, including making the peak current limit accurate in both sync and dynamic sleep modes. If the scheme is carefully designed, the dynamic sleep current limit gives the best load transient response.