Dynamic Drive-Current Transmission Circuit for USB Eye Pattern Stability

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Solution Overview

Problem

Existing USB transmission circuits face challenges in improving eye pattern characteristics due to degradation caused by resistance and capacitance in transmission paths, particularly in long cables, which complicates timing adjustments and affects signal quality.

Innovation Solution

A transmission circuit design that includes a current output circuit with switch elements to dynamically adjust drive current, increasing it during specific n-bit periods after the logic level inversion, thereby simplifying timing adjustments and enhancing eye pattern characteristics while reducing signal quality degradation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the drive current is increased to improve eye pattern characteristics, then the transmission signal quality deteriorates due to timing adjustment complexity

Engineering Contradiction:
Improveeye pattern characteristicsVSAvoidtiming adjustment complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent implements dynamic current adjustment by switching between a first current value and a second current value based on the logic level transitions of the transmission signal. The current output circuit changes its output current dynamically in response to signal transitions, allowing optimization of eye pattern characteristics without requiring complex static timing adjustments for multiple driver configurations.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the current parameter of the driver circuit based on the transition state of the transmission signal. By detecting logic level inversions and adjusting the drive current accordingly (switching between first and second current values), the system optimizes signal transmission quality while maintaining simple timing control architecture.

Inventive Principle:
Principle #35Parameter changes

2Power

If multiple drivers are provided in parallel to increase drive current, then the timing adjustment becomes complicated due to multiple switch timing relationships

Engineering Contradiction:
Improvedrive currentVSAvoidtiming adjustment complexity
Core Design Contradiction:
PowerVSDevice complexity

Solution Approach 1:

Instead of using multiple parallel drivers with fixed timing relationships, the patent employs a single driver with dynamically adjustable current output. The current output circuit responds dynamically to signal transitions by switching between different current values, achieving the power enhancement of multiple drivers while maintaining the timing simplicity of a single driver configuration.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent achieves increased drive current capability by changing the current parameter of a single driver based on signal transition detection, rather than using multiple drivers in parallel. This parameter-based approach provides the same power enhancement as multiple drivers without the associated timing adjustment complexity.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS10419247B2Transmission circuit, integrated circuit device and electronic device
Publication Date: 2019.09.17 SEIKO EPSON CORP
  • US10419247B2 patent drawing
  • US10419247B2 patent drawing
  • US10419247B2 patent drawing

AI summary

A transmission circuit includes a current output circuit that outputs a current to a first node, a first switch element provided between the first node and a first signal line, and a second switch element provided between the first node and a second signal line. When a transmission signal is at a first logic level, the first switch element is ON and the second switch element is OFF. When the transmission signal is at a second logic level, the first switch element is OFF and the second switch element is ON. The current output circuit outputs a second current in an n-bit period after the logic level of the transmission signal is inverted, and outputs a first current after the n-bit period.