Dynamic Data Buffer Memory Module for Bus Load Reduction
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Solution Overview
Problem
The existing computer systems face challenges in increasing memory capacity without overloading the memory bus, as the CPU's fixed set of pins limits the expansion of memory modules.
Innovation Solution
A double high memory module with multiple registering clock drivers and dynamic data buffers is introduced, which allows for extended memory capacity by minimizing the load on the command and address channel while maintaining efficient data access without increasing the data channel load.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If more memory modules are used to increase memory capacity, then the memory capacity is improved, but the loading on the memory bus increases causing performance degradation
Solution Approach 1:
The memory module is divided into multiple independent memory chip sets, with each set having its own dedicated data buffer. This segmentation allows parallel access to multiple memory chips through a single data buffer, effectively increasing memory capacity while maintaining constant data channel load by processing multiple chips simultaneously without requiring additional data channel resources.
2Quantity of substance
If the number of memory chips is increased, then the memory capacity is improved, but the complexity of controlling all memory chips increases
Solution Approach 1:
A data buffer is introduced as an intermediary component between the memory chips and the data channel. This data buffer manages and coordinates access to multiple memory chips, absorbing the complexity of controlling numerous chips while presenting a simplified interface to the data channel. The data buffer handles chip selection, data routing, and timing coordination, thereby increasing memory capacity without proportionally increasing control complexity at the system level.
3Productivity
If more memory chips are accessed simultaneously, then the memory capacity utilization is improved, but the data channel load increases
Solution Approach 1:
Multiple memory chips are merged into a single logical access unit through the data buffer. The data buffer combines the data outputs from multiple memory chips and presents them as a unified data stream to the data channel. This merging allows simultaneous access to multiple memory chips while maintaining constant data channel load, as the data buffer handles the aggregation and coordination internally without requiring proportional increases in data channel bandwidth.
Data Source
AI summary
A memory module uses dynamic data buffers for providing extended capacity for computing systems. The memory module comprises an external interface having a first set of data pins and a second set of data pins. The memory module includes a first set of memory chips and a second set of memory chips. The memory module includes a first registering clock driver to control the first set of memory chips and a second registering clock driver to control the second set of memory chips. The memory module further includes a first data buffer to connect the first set of memory chips to the first set of data pins and a second data buffer to connect the second set of memory chips to the second set of data pins.