Dynamic Data Lane Control for Display Power Reduction
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Solution Overview
Problem
Existing data transfer methods in flat panel displays, such as liquid crystal display devices, face challenges in reducing power consumption due to continuous electric current flowing through transmitter and receiver circuits, particularly with high-speed serial interfaces like LVDS, which leads to increased power consumption from termination resistors and requires complex clock lane configurations for varying transfer speeds.
Innovation Solution
A data transfer circuit that dynamically determines the number of data lanes to use based on the amount of data to be transferred within a predetermined time period, deactivates unused lanes to minimize power consumption, and maintains a consistent transfer rate across all lanes, eliminating the need for individual clock lanes for each lane.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the number of data lanes is increased to improve data transfer speed, then the data transfer rate is improved, but the power consumption increases due to continuous current flow through more lanes
Solution Approach 1:
The patent implements dynamic switching between different numbers of active data lanes based on the data transfer rate requirements. The system can switch from using all lanes for high-speed transfer to using fewer lanes when lower speed is sufficient, thereby adapting the power consumption to the actual performance needs rather than maintaining all lanes active continuously
Solution Approach 2:
The patent changes the operational parameter of the data lanes by selectively activating or deactivating specific lanes based on the required transfer rate. This allows the system to adjust the number of active lanes as a variable parameter, optimizing the balance between transfer speed and power consumption for different operating conditions
2Productivity
If different transfer speeds are implemented for different transmitter sections, then the data transfer efficiency is improved, but the circuit complexity increases due to requirement of multiple clock lanes
Solution Approach 1:
The patent merges the clock signal distribution across all data lanes by using a single common clock lane that synchronizes all lanes operating at the same speed. This eliminates the need for separate clock lanes for each transmitter section, thereby reducing circuit complexity while still enabling different transfer speeds through lane selection rather than individual clock control
Solution Approach 2:
The single clock lane serves multiple functions by providing synchronization for any combination of active data lanes. This universal clock signal can support all lanes operating together at full speed or any subset of lanes at reduced speed, making the clock infrastructure multi-functional and adaptable to different operating modes without requiring separate clocking circuits
Data Source
AI summary
The timing controller determines the number of data lanes (11, 12, 13), which are used to transfer data, based on information in relation to an amount of data to be transferred during a predetermined time period. Out of the plurality of data lanes (11, 12, 13), the determined number of data lane(s) (11, 12, 13) are used to transfer data. Further, a data lane(s) (11, 12, 13) which is not used in the data transfer is deactivated.