Dynamic Data Link Clock Frequency Adjustment Without Downtime

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Solution Overview

Problem

Current computing devices face performance issues due to downtime and latency when changing clock frequencies for the data link layer, leading to potential queue overflow or underflow events during power management features or modes.

Innovation Solution

Implementing a method where processors switch FIFO queues from pacing mode to asynchronous mode without deactivating the data link, allowing for dynamic frequency changes of MAC clocks while maintaining data link activity, and then returning to pacing mode as needed.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If the data link is taken down, suspended, or deactivated to change clock frequency, then the clock frequency can be changed, but downtime and latency are introduced

Engineering Contradiction:
Improveclock frequency adaptabilityVSAvoiddowntime and latency
Core Design Contradiction:
Adaptability or versatilityVSLoss of time

Solution Approach 1:

The system switches FIFO queues to asynchronous mode before changing the clock frequency, preparing the data link to handle frequency transitions without interruption. This preliminary mode change allows the frequency adjustment to occur without taking down the data link, thus avoiding downtime and latency while maintaining clock frequency adaptability.

Inventive Principle:
Principle #10Preliminary action

2Adaptability or versatility

If the data link is taken down, suspended, or deactivated to change clock frequency, then the clock frequency can be changed, but data transmission is interrupted

Engineering Contradiction:
Improveclock frequency adaptabilityVSAvoiddata transmission continuity
Core Design Contradiction:
Adaptability or versatilityVSProductivity

Solution Approach 1:

The system maintains the data link in an active state throughout the clock frequency change process by using asynchronous FIFO queue mode. This allows data transmission to continue uninterrupted while the clock frequency is adjusted, ensuring both frequency adaptability and continuous productivity without transmission interruptions.

Inventive Principle:
Principle #20Continuity of useful action

3Productivity

If the data link remains active during clock frequency changes, then data transmission continues, but queue overflow or underflow events may occur

Engineering Contradiction:
Improvedata transmission continuityVSAvoidqueue stability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The system dynamically switches the FIFO queue mode from pacing to asynchronous during clock frequency changes. This dynamic adaptation allows the queue handling mechanism to adjust to the frequency transition, preventing overflow or underflow events while maintaining continuous data transmission, thus ensuring both productivity and reliability.

Inventive Principle:
Principle #15Dynamics

4Loss of time

If FIFO queues are switched to asynchronous mode for frequency changes, then downtime is eliminated, but system complexity increases

Engineering Contradiction:
Improvedowntime eliminationVSAvoidqueue mode management
Core Design Contradiction:
Loss of timeVSDevice complexity

Solution Approach 1:

The system changes the operational parameter of FIFO queues from pacing mode to asynchronous mode temporarily during clock frequency adjustments. This parameter change enables downtime elimination while the increased complexity is confined to a controlled, temporary state change rather than a permanent system architecture modification.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS20250103090A1Devices, systems, and methods for dynamically changing frequencies of clocks for the data link layer without downtime
Publication Date: 2025.03.27 ATI TECHNOLOGIES ULC
  • US20250103090A1 patent drawing
  • US20250103090A1 patent drawing
  • US20250103090A1 patent drawing

AI summary

An exemplary method for dynamically changing frequencies of clocks for the data link layer without downtime involves switching a first queue on a first end of a data link and a second queue on a second end of the data link from a pacing mode to an asynchronous mode. The exemplary method also involves modifying a frequency of a clock associated with the data link. The exemplary method further involves returning the first queue and the second queue from the asynchronous mode to the pacing mode upon modifying the frequency of the clock. Various other devices, systems, and methods are also disclosed.