Dynamic Data-Link Selection for GPIO Pin Reduction
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Solution Overview
Problem
The high demand for GPIO pins for inter-processor communication (IPC) in mobile devices increases manufacturing costs and limits availability for other system-level peripheral interfaces, as each symmetric sideband signal requires two GPIOs for transmission and reception, leading to a significant number of pins being necessary for IPC signaling.
Innovation Solution
A dynamic data-link selection apparatus that includes a communication interface circuit and a processing circuit, capable of detecting the type of data to be transmitted and configuring a physical interconnect line for either serial bus communication or virtual general purpose input/output communication protocol, allowing for efficient use of pins by determining whether to transmit data using a serial bus or virtual GPIO protocol based on priority settings, data amount, or transmission time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dedicated GPIO pins are used for each symmetric sideband signal in IPC communication, then reliable inter-processor communication is achieved, but the number of required GPIO pins increases significantly, increasing manufacturing cost and limiting availability for other interfaces
Solution Approach 1:
The patent merges multiple communication protocols (I2C and GPIO) onto a single shared physical bus. The application processor can dynamically select which protocol to use on the shared bus, eliminating the need for separate dedicated pins for each protocol. This combining approach reduces the total pin count while maintaining the functionality of both I2C memory access and GPIO-based IPC communication.
Solution Approach 2:
The patent implements dynamic protocol selection where the application processor can switch between I2C and GPIO protocols on the shared bus based on real-time communication needs. This dynamic multiplexing allows the same physical pins to serve different communication functions at different times, reducing the static pin requirement while ensuring reliable communication for both protocols when needed.
2Adaptability or versatility
If multiple dedicated communication modules are provided for different protocols, then protocol-specific communication requirements are met, but the device complexity and manufacturing cost increase
Solution Approach 1:
The patent creates a universal shared bus that can operate with multiple communication protocols (I2C and GPIO). Instead of providing separate dedicated modules for each protocol, a single multi-functional bus is designed that can be configured to support different protocols as needed. This universal approach reduces manufacturing complexity and cost while maintaining adaptability to various communication requirements.
Solution Approach 2:
The patent changes the operational parameters of the shared bus dynamically based on the selected protocol. When I2C protocol is selected, the bus operates with I2C-specific timing and signaling parameters; when GPIO protocol is selected, it switches to GPIO parameters. This parameter switching capability allows a single physical bus to serve multiple protocol requirements without requiring separate dedicated hardware for each protocol.
3Device complexity
If a shared bus is used for both I2C and GPIO protocols, then pin availability is improved, but protocol conflict and data transmission errors may occur
Solution Approach 1:
The patent implements preliminary protocol selection and configuration before actual data transmission begins. The application processor determines which protocol (I2C or GPIO) should be used on the shared bus and configures the bus parameters accordingly before initiating communication. This advance configuration prevents protocol conflicts during transmission by ensuring the bus is properly set up for the selected protocol before any data is sent.
Solution Approach 2:
The patent incorporates feedback mechanisms to monitor the shared bus communication status and detect any protocol conflicts or transmission errors. The system can detect when the wrong protocol is being used on the bus and trigger appropriate error handling or protocol switching. This feedback ensures data transmission reliability by continuously verifying that the correct protocol is active on the shared bus.
Data Source
AI summary
A hybrid virtual general purpose input/output (VGI) architecture is provided including a pair of devices coupled through a high-speed cable. The architecture enables a device to communicate sideband signals through the high-speed cable using two pins coupled to respective interconnects of a bus. In an aspect, the architecture may implement link selection without protocol consolidation where the device may configure the two pins for I2C (or I3C) signaling or VGI signaling. In another aspect, the architecture may implement link bridging with protocol consolidation where the device may transmit (or receive) I2C (or I3C) signals through the high-speed cable using a VGI communication protocol.