Dynamic Data-Plane Resource Shadowing for Network Devices

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Solution Overview

Problem

Traditional memory and disk caching techniques are ineffective for data-plane resources in networking equipment due to unpredictable access patterns and the massive, sparsely populated nature of these resources, leading to high latency and inefficiencies in packet processing.

Innovation Solution

Dynamic resource shadowing operations that maintain local shadow copies of data-plane resources in host CPU memory to reduce reliance on bus interconnect access, improving throughput and reducing latency by up to ten-fold.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of time

If traditional memory caching techniques are used for data-plane resources, then cache memory can be implemented, but the unpredictable access patterns and sparsity of data-plane resources make locality of reference ineffective, resulting in high latency

Engineering Contradiction:
Improveaccess latencyVSAvoidpacket processing throughput
Core Design Contradiction:
Loss of timeVSProductivity

Solution Approach 1:

The patent creates shadow copies of data-plane resources (MAC address tables, FIB tables, RIB tables, ACL tables) in host CPU memory. These shadow copies are maintained synchronously with the actual data-plane resources, allowing the host CPU to access local copies instead of fetching from data-plane devices over the bus interconnect. This copying approach resolves the latency issue by providing local access while maintaining data consistency through synchronous updates.

Inventive Principle:
Principle #26Copying

Solution Approach 2:

The system proactively maintains shadow copies of data-plane resources in host CPU memory before they are needed for packet processing. By pre-positioning the data in local memory and maintaining it synchronously, the system eliminates the need for real-time bus transactions during packet processing, thereby reducing latency and improving throughput.

Inventive Principle:
Principle #10Preliminary action

2Speed

If data-plane resources are accessed synchronously and immediately by host CPU, then packet processing speed is improved, but the massive quantities and large memory map area of data-plane resources make traditional caching techniques impractical

Engineering Contradiction:
Improvepacket processing speedVSAvoidmemory management complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

Instead of implementing complex caching algorithms to manage large data-plane resources, the patent creates simplified shadow copies in host CPU memory. These shadow copies mirror the data-plane resources and are maintained through synchronous update mechanisms, reducing memory management complexity while enabling fast local access for packet processing.

Inventive Principle:
Principle #26Copying

Solution Approach 2:

The shadow copies act as an intermediary layer between the host CPU and the actual data-plane resources. This intermediary allows the host CPU to access data locally with synchronous updates, eliminating the need for complex direct memory management of large data-plane resources while maintaining access speed.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Reliability

If data-plane resources are stored in data-plane devices with on-chip or near-chip resources, then data-plane functionality is improved, but host CPU access requires bus interconnect transactions, increasing latency

Engineering Contradiction:
Improvedata-plane resource reliabilityVSAvoidbus access latency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent creates shadow copies of data-plane resources in host CPU memory that can be accessed locally without bus transactions. These shadow copies are maintained synchronously with the actual data-plane resources, ensuring data integrity while eliminating bus access latency for host CPU operations.

Inventive Principle:
Principle #26Copying

Solution Approach 2:

By pre-positioning data-plane resource copies in host CPU memory and maintaining them synchronously, the system prepares data for future host CPU access operations. This preliminary action ensures that when the host CPU needs to access data-plane resources, the data is already available in local memory, eliminating bus transaction latency.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS11537432B2Dynamic data-plane resource shadowing
Publication Date: 2022.12.27 CISCO TECHNOLOGY INC
  • US11537432B2 patent drawing
  • US11537432B2 patent drawing
  • US11537432B2 patent drawing

AI summary

Embodiments of the present disclosure are directed to dynamic shadow operations configured to dynamically shadow data-plane resources in a network device. In some embodiments, the dynamic resource shadow operations are used to locally maintain a shadow copy of data plane resources to avoid having to read them through a bus interconnect. In other embodiments, the dynamic shadow framework is used to provide memory protection for hardware resources against SEU failures. The dynamic shadow framework may operate in conjunction with adaptive memory scrubbing operations. In other embodiments, the dynamic shadow infrastructure is used to facilitate fast boot-up and fast upgrade operations.