Dynamic Data Routing Among Multicore Processors

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

In multi-core systems, existing direct memory access (DMA) controllers complicate bus system architecture and require additional operating systems to change data transfer paths between cores, making them inefficient for data routing.

Innovation Solution

A data routing apparatus that generates configuration information using program counters from each core to dynamically change data transfer paths among multiple cores, eliminating the need for multiple DMA controllers and additional operating systems, and includes a configuration information generating unit, switching units, and a profiling unit to optimize data transfer.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If a DMA controller is used to transfer data between cores in a multi-core system, then data transfer can be performed independently of the CPU, but the bus system architecture becomes complicated and additional operating systems are needed to change data transfer paths

Engineering Contradiction:
Improvedata transfer efficiencyVSAvoidbus system architecture complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent merges the functions of multiple DMA controllers into a single reconfigurable data transfer apparatus. By using a unified controller with dynamic path routing capabilities, the system eliminates the need for separate DMA controllers for each core pair, thereby simplifying the bus system architecture while maintaining efficient data transfer between multiple cores

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent implements dynamic reconfiguration of data transfer paths through a reconfigurable router that can change routing topology based on real-time requirements. This dynamic capability allows a single controller to handle multiple data transfer scenarios without requiring additional hardware or operating system interventions, resolving the contradiction between transfer efficiency and architectural complexity

Inventive Principle:
Principle #15Dynamics

2Productivity

If multiple DMA controllers are provided to handle data transfer between multiple cores, then data transfer independence from CPU is maintained, but the system complexity and cost increase

Engineering Contradiction:
Improveparallel data transfer capabilityVSAvoidnumber of DMA controllers
Core Design Contradiction:
ProductivityVSQuantity of substance

Solution Approach 1:

The patent creates a universal data transfer apparatus that can serve multiple core pairs simultaneously. The reconfigurable router enables a single controller to dynamically adapt its routing paths to handle different data transfer requirements between various core combinations, providing multi-functional capability that replaces what would otherwise require multiple dedicated DMA controllers

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent segments the data transfer function into independent routing paths within a unified controller. By dividing the routing logic into separate configurable paths that can be activated independently, the system maintains parallel data transfer capabilities while consolidating the physical controller infrastructure, thus reducing the total number of DMA controllers needed

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS9141579B2Apparatus and method for routing data among multiple cores
Publication Date: 2015.09.22 SAMSUNG ELECTRONICS CO LTD
  • US9141579B2 patent drawing
  • US9141579B2 patent drawing
  • US9141579B2 patent drawing

AI summary

An apparatus and method for routing data among multicores that is capable of reconfiguring the connection among the multicores are provided. The apparatus includes a configuration information generating unit and at least one switching unit. The configuration information generating unit is configured to generate configuration information that indicates a local network connection among the multicores based on a program counter received from each of the multicores. The at least one switching unit is configured to change a data transfer path among the multicores based on the configuration information.