Dynamic Datapath Chaining for Low-Power Programmable Logic
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Solution Overview
Problem
Conventional programmable logic devices (PLDs) and field-programmable gate arrays (FPGAs) face challenges such as high power consumption and large silicon area, limiting their efficiency in implementing additional peripherals and increasing development costs and complexity in electronic systems.
Innovation Solution
The introduction of a Universal Digital Block (UDB) architecture that combines PLDs with a datapath module, enabling dynamic chaining and unchaining of arithmetic operations based on configuration data and clock cycles, allowing for customizable digital functions and efficient use of silicon space.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional PLDs and FPGAs are used to implement additional peripherals, then functional versatility is improved, but power consumption and silicon area increase
Solution Approach 1:
The patent implements a universal datapath structure that can dynamically perform multiple arithmetic operations (addition, subtraction, multiplication, division) and logical functions through reconfiguration. This single versatile datapath replaces multiple dedicated functional units, reducing both silicon area and power consumption while maintaining the ability to implement various peripherals and digital functions.
Solution Approach 2:
The datapath structure employs dynamic reconfiguration capabilities where the same hardware resources can be dynamically allocated and reconfigured for different functions based on system requirements. This dynamic nature allows the system to adapt to different peripheral implementations without permanently dedicating resources, thereby reducing overall power consumption and silicon area usage.
2Adaptability or versatility
If conventional PLDs and FPGAs are used to implement additional peripherals, then functional versatility is improved, but silicon area increases
Solution Approach 1:
The patent implements a universal datapath structure that can dynamically perform multiple arithmetic operations (addition, subtraction, multiplication, division) and logical functions through reconfiguration. This single versatile datapath replaces multiple dedicated functional units, reducing both silicon area and power consumption while maintaining the ability to implement various peripherals and digital functions.
Solution Approach 2:
The patent combines multiple arithmetic logic units and functional elements into a single integrated datapath structure. By merging these functions into one reconfigurable unit, the patent significantly reduces the total silicon area required compared to having separate dedicated units for each function, while still providing the capability to implement various peripherals.
3Device complexity
If coarse grained digital programmability is used in PSoC architectures, then device complexity is reduced, but adaptability and versatility are limited
Solution Approach 1:
The datapath structure employs dynamic reconfiguration capabilities where the same hardware resources can be dynamically allocated and reconfigured for different functions based on system requirements. This dynamic nature allows the system to adapt to different peripheral implementations without permanently dedicating resources, thereby reducing overall power consumption and silicon area usage.
Data Source
AI summary
A system includes a plurality of datapaths, each having structural arithmetic elements to perform various arithmetic operations based, at least in part, on configuration data. The system also includes a configuration memory coupled to the datapaths, the configuration memory to provide the configuration data to the datapaths, which causes the datapaths to collaborate when performing the arithmetic operations.