Dynamic DC Offset Correction in Ethernet Receiver ADCs
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Solution Overview
Problem
Conventional DC offset correction methods are unsuitable for systems like 10 Mb/s Ethernet receivers due to the continuous non-static waveform and limited ADC output range, making it difficult to determine an accurate offset.
Innovation Solution
A digital logic-based offset corrector system that utilizes a comparator, counter, summation block, offset generator, and offset applier to calculate and apply a DC offset during silent periods, allowing for dynamic DC offset correction without the need for analog circuitry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional analog and digital circuitry is used for DC offset correction, then the correction can be applied to systems with static waveforms, but it cannot accurately determine offset in systems with continuous non-static waveforms like 100 Mb/s and Gigabit Ethernet
Solution Approach 1:
The patent implements dynamic DC offset correction by continuously monitoring ADC outputs during active signal periods and updating offset values in real-time, rather than relying on static calibration during silent periods. This allows the system to adapt to changing signal conditions in 100 Mb/s and Gigabit Ethernet while maintaining accurate offset correction.
Solution Approach 2:
The patent changes the operational parameters of the DC offset correction system by eliminating the requirement for silent periods and nominal voltage levels. Instead, it uses the continuous non-static waveform characteristics of modern Ethernet standards to dynamically calculate and apply offset corrections, making the system compatible with higher-speed Ethernet implementations.
2Measurement precision
If DC offset correction is performed during active signal periods, then accurate correction can be achieved in systems without silent periods, but the correction cannot rely on nominal voltage level detection
Solution Approach 1:
The patent employs feedback mechanisms where the ADC outputs during active signal periods are continuously monitored and fed back to the DC offset correction logic. This feedback loop enables the system to dynamically adjust offset values based on actual signal conditions, achieving accurate correction without relying on nominal voltage level detection or silent periods.
Solution Approach 2:
The patent performs preliminary offset correction calculations during active signal periods before the actual data processing occurs. By proactively determining and applying offset values during the signal reception window, the system prepares corrected data for subsequent processing without requiring separate calibration phases.
3Ease of manufacture
If digital logic-based correction is used instead of analog circuitry, then the system becomes more portable to ASIC designs, but the complexity of handling continuous non-static waveforms increases
Solution Approach 1:
The patent replaces analog circuitry with digital logic-based DC offset correction. By implementing the correction functionality entirely in the digital domain using standard digital logic components and algorithms, the system becomes much more portable to ASIC designs while maintaining the capability to handle continuous non-static waveforms through software-configurable correction parameters.
Data Source
AI summary
A method for providing dynamic DC offset correction is provided. The method includes receiving a plurality of uncorrected samples. A determination is made regarding whether a specified number of consecutive uncorrected samples that correspond to a nominal voltage level has been received. When the specified number of consecutive uncorrected samples that correspond to the nominal voltage level has been received, an offset is generated based on an actual voltage level for each of the consecutive uncorrected samples.