Dynamic Addressing Decimation Filter for Lower-Power Multi-Bit ADCs
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Solution Overview
Problem
Traditional decimation filters in incremental analog-digital converters (IADCs) consume high power and occupy large areas, especially when implemented with multi-bit quantizers, due to the need for a large number of physical sub-decimation filters equal to the total number of quantizer levels, which increases the chip thermal budget and area.
Innovation Solution
A dynamic decimation filtering approach is implemented using a multi-bit analog modulator paired with a properly configured decimation filter, reducing the number of physical sub-decimation filters required, thereby minimizing power consumption and chip area through proper circuit architecture and dynamic addressing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional decimation filters are used with multi-bit quantizers, then conversion rate and resolution are improved, but power consumption and chip area increase significantly
Solution Approach 1:
The decimation filter is divided into multiple sub-decimation filters, each handling a specific portion of the quantizer levels. This segmentation allows parallel processing with reduced complexity per filter, lowering overall power consumption while maintaining high conversion resolution through combined output.
Solution Approach 2:
A dynamic addressing mechanism is implemented that adaptively selects and activates only the necessary sub-decimation filters based on the current signal characteristics and quantizer level requirements. This dynamic approach reduces the number of active filters at any given time, significantly decreasing power consumption while preserving measurement precision when needed.
2Measurement precision
If the number of quantizer levels M increases to improve resolution, then conversion accuracy is improved, but the number of physical sub-decimation filters N must increase proportionally, increasing chip area
Solution Approach 1:
Each sub-decimation filter is designed with multi-functionality to handle multiple quantizer level ranges. Through the dynamic addressing mechanism, the same physical filter can be assigned to different level ranges at different times, allowing a smaller number of physical filters N to support a larger number of quantizer levels M, thus reducing chip area while maintaining high resolution.
Solution Approach 2:
The system introduces a time dimension to the filter allocation problem. Instead of requiring N physical filters for M quantizer levels simultaneously, the dynamic addressing allows filters to be reused across different time intervals for different level ranges. This temporal multiplexing effectively reduces the spatial requirement (chip area) while maintaining the capability to handle high quantizer levels for improved resolution.
3Reliability
If more physical sub-decimation filters are used to handle higher quantizer levels, then filtering accuracy is improved, but power demand and device complexity increase
Solution Approach 1:
The dynamic addressing mechanism adaptively configures which sub-decimation filters are active based on real-time signal characteristics and quantizer level requirements. This dynamic configuration maintains filtering accuracy by selecting the appropriate filters for the current operating conditions while reducing the number of simultaneously active filters, thereby lowering power demand and effective device complexity.
Solution Approach 2:
The system incorporates automatic configuration capabilities where the decimation filter architecture self-adjusts its active components based on the input signal properties and quantizer level requirements. This self-service approach maintains optimal filtering accuracy without requiring external complex control, reducing overall device complexity while preserving reliability.
Data Source
AI summary
Various embodiments of the present technology may comprise a method, apparatus or system for dynamic addressing decimation filtering. In various embodiments, the apparatus comprises an analog modulator and a multi-bit dynamically addressing decimation filter. By pairing an analog modulator with the proper configuration with a multi-bit dynamically addressing decimation filter with the proper matching number of physical sub decimation filters, decimation filtering can be completed with a smaller number of physical sub decimation filters “N” than the quantizer level “M.”