Dynamic Delay Calibration for Time-Multiplexed Bus Systems

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Solution Overview

Problem

High-speed communication systems face challenges in maintaining signal quality due to uncertainty in signal arrival times caused by internal and external delays, leading to poor signal quality or transmission failure, especially at higher speeds, and existing solutions require precise circuits and trimming, increasing production costs.

Innovation Solution

The implementation of an automatic adjustment procedure that allows devices to self-calibrate by estimating and adjusting delays using a time-multiplexed clock and data protocol, enabling devices to synchronize communications without the need for precise circuits, thereby reducing production costs and power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If high-speed data transmission is implemented, then communication speed is improved, but signal quality deteriorates due to timing uncertainty from internal and external delays

Engineering Contradiction:
Improvedata transmission speedVSAvoidsignal quality
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The patent performs delay calibration before high-speed data transmission by having the slave device write test values to the bus at different timing offsets. The master device reads these values and determines the optimal sampling time, establishing preliminary timing parameters that compensate for internal and external delays before actual data communication begins.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent implements a feedback mechanism where the master device reads back values written by the slave device and uses this information to determine the optimal sampling timing. The system iteratively adjusts timing based on the read-back values until the correct sampling point is identified, then applies this timing information to ensure reliable high-speed communication.

Inventive Principle:
Principle #23Feedback

2Manufacturing precision

If precise circuits and trimming are used to reduce delay variability, then manufacturing precision is improved, but production cost increases

Engineering Contradiction:
Improvedelay precisionVSAvoidproduction cost
Core Design Contradiction:
Manufacturing precisionVSEase of manufacture

Solution Approach 1:

The patent enables devices to self-calibrate their timing parameters through automated delay calibration procedures. The slave device and master device work together to determine optimal timing without requiring external precision trimming or specialized precision circuits, allowing standard manufacturing processes to be used while achieving precise timing through software-controlled calibration.

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The patent changes the timing parameter dynamically by allowing the slave device to write values at different timing offsets and the master device to sample at different times. This parameter adjustment approach replaces the need for precise physical circuit design with flexible software-controlled timing parameters that can be optimized after manufacturing.

Inventive Principle:
Principle #35Parameter changes

3Reliability

If delay calibration is performed to maintain signal integrity, then reliability is improved, but communication time increases due to calibration overhead

Engineering Contradiction:
Improvesignal integrityVSAvoidcalibration time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The delay calibration is performed once during initialization or setup phase before actual data communication begins. The timing parameters determined during this preliminary calibration are then reused for subsequent high-speed data transmission, so the time overhead occurs only once rather than continuously during normal operation.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS11294837B2Dynamic delay calibration of devices attached to bus systems utilizing time-multiplexed clock and data lines
Publication Date: 2022.04.05 GOOGLE LLC
  • US11294837B2 patent drawing
  • US11294837B2 patent drawing
  • US11294837B2 patent drawing

AI summary

Systems and methods for performing dynamic adaption and correction for internal delays in devices connected to a common time-multiplexed bus. The methods allow devices to operate reliably at a higher bus frequency by correcting for inherent and unknown delays within the components and in the system by measuring the actual delays using multiple readings with this bus. The inherent noise and jitter are utilized to increase the precision of the measurements thereby essentially using this uncertainty as a self-dithering for increased resolution in the measurements. During adaption, the delays may be adjusted in multiple step sizes for a faster adaption time.