Dynamic Programmable Delay Selection Circuit for DDR Memory
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Solution Overview
Problem
Existing memory controllers face challenges in generating accurate asymmetric delays for DDR DRAM operations due to manufacturing, voltage, and temperature variations, which can lead to glitches and erroneous data capture.
Innovation Solution
A system comprising a measurement circuit to assess operating conditions, a control circuit to convert measurement values into control signals, and a delay circuit to adjust signal delays based on these conditions, ensuring accurate and adaptive delay generation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If fixed delays are generated using a delay line with logic devices, then delay generation is achieved, but manufacturing process variations, voltage variations, and temperature variations cause delay inaccuracies
Solution Approach 1:
The delay line is made dynamically adjustable by introducing a control signal that can modify the delay characteristics of the logic devices in real-time, allowing the system to adapt to manufacturing variations, voltage changes, and temperature fluctuations rather than being fixed at design time
Solution Approach 2:
The invention changes the operational parameters of the delay line by applying a control signal that adjusts the delay amount based on measured operating conditions (voltage, temperature), thereby compensating for variations and maintaining accurate delays under different conditions
2Adaptability or versatility
If tap selection on the delay line is changed, then different delay values are achieved, but inopportune tap changes cause glitches on the strobe line
Solution Approach 1:
The system uses feedback by measuring actual operating conditions (voltage, temperature) and using these measurements to determine when and how to adjust the delay line tap selection, ensuring changes occur only when appropriate and safe to avoid glitches
Solution Approach 2:
The control circuit preliminarily determines the appropriate tap selection based on measured operating conditions before making the actual delay adjustment, ensuring that tap changes are planned and executed at appropriate times to prevent strobe line glitches
3Productivity
If asymmetric delays are generated for input and output strobe signals, then optimal DDR DRAM operation is achieved, but delay inaccuracies lead to erroneous data capture
Solution Approach 1:
The invention dynamically adjusts the delay parameters for both input and output strobe signals based on measured operating conditions, maintaining the desired asymmetric delay relationship while compensating for variations to ensure accurate data capture
Solution Approach 2:
The system employs feedback by continuously measuring operating conditions and using this information to adjust the asymmetric delays, ensuring that both the input and output strobe delays remain accurate under varying conditions while maintaining their asymmetric relationship for optimal DDR DRAM performance
Data Source
AI summary
A controller may include a measurement circuit configured to generate a proxy signal representing delay variations in the controller. The measurement circuit may also generate a measurement value from the proxy signal. A control circuit may be configured to convert the measurement value into a control value. A delay circuit may be adjusted by the control value to alter an amount of delay of a signal.