Dynamic Delay Time Adjustment in Storage Memory Controllers

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Solution Overview

Problem

Existing storage devices face challenges in optimizing the delay time for writing data, leading to inefficiencies in memory latency and throughput.

Innovation Solution

A storage device with a memory controller that determines a delay time based on various parameters, such as buffer memory usage and elapsed time, using a genetic algorithm to optimize the delay model and improve performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If a fixed delay time is used for writing data to the buffer memory, then the storage device can operate with simple control logic, but the memory latency and throughput cannot be optimized

Engineering Contradiction:
ImprovethroughputVSAvoidcontrol complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The delay time is changed from a fixed value to a dynamic value that varies based on buffer memory usage conditions. The memory controller adjusts the delay time according to real-time buffer occupancy levels, allowing the system to optimize throughput under different operating conditions while maintaining manageable control complexity through predefined adjustment rules.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The delay time parameter is modified based on changes in buffer memory usage parameters. When buffer usage exceeds certain thresholds, the delay time parameter is automatically adjusted to prevent overflow and optimize performance, enabling the system to adapt to varying workload conditions without complex control mechanisms.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If the delay time is extended to prevent buffer overflow, then data loss is reduced, but the memory latency increases

Engineering Contradiction:
Improvedata loss preventionVSAvoidmemory latency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The delay time is dynamically adjusted based on current buffer memory usage conditions rather than being extended constantly. When buffer usage is low, the delay time is reduced to minimize latency. When buffer usage approaches capacity thresholds, the delay time is extended to prevent overflow, thus achieving reliable data loss prevention only when necessary without incurring constant latency penalties.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system continuously monitors buffer memory usage and continuously adjusts the delay time to maintain optimal operation. This continuous adaptation ensures that the delay time is extended only when needed to prevent data loss, rather than being constantly extended, thereby minimizing overall memory latency while maintaining reliability.

Inventive Principle:
Principle #20Continuity of useful action

3Speed

If the delay time is reduced to improve response speed, then memory latency decreases, but the risk of buffer overflow increases

Engineering Contradiction:
Improveresponse speedVSAvoidbuffer overflow risk
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The delay time is dynamically adjusted based on real-time buffer memory usage conditions. When buffer usage is low, the delay time is reduced to improve response speed. When buffer usage approaches capacity thresholds, the delay time is automatically extended to prevent overflow, thus achieving fast response speed under normal conditions while maintaining reliability under high-load conditions.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system uses feedback from buffer memory usage monitoring to adjust the delay time. The memory controller continuously receives feedback on buffer occupancy levels and uses this feedback to modulate the delay time accordingly, reducing it when buffer space is available to improve speed and increasing it when buffer space is limited to prevent overflow and maintain reliability.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS12307127B2Storage device and host device for optimizing model for calculating delay time of the storage device
Publication Date: 2025.05.20 SK HYNIX INC
  • US12307127B2 patent drawing
  • US12307127B2 patent drawing
  • US12307127B2 patent drawing

AI summary

A storage device according to the present technology may include a memory device for storing data, a buffer memory configured to temporarily store data to be stored in the memory device, and a memory controller configured to determine a delay time based on a plurality of parameters upon receipt of a write request from a host, and transmit a data request to the host after the delay time has elapsed.