Dynamic Demultiplexer for High Frame Rate Displays
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Solution Overview
Problem
Existing display driver circuitry for electronic devices often results in low frame rates or unsatisfactory display performance due to inadequate supply of data signals to pixels, particularly when care is not taken in configuring gate and data lines.
Innovation Solution
The implementation of demultiplexer circuitry that dynamically configures during data loading and pixel sensing operations, using alternating even and odd data lines organized in pairs with mirrored layouts, and staggering control signals to overlap gate signal assertions across rows, thereby enhancing data loading accuracy and reducing capacitive coupling artifacts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional display driver circuitry is used with standard data line configuration, then the display can operate, but frame rates are too low and display performance is unsatisfactory
Solution Approach 1:
The display is divided into multiple zones with different refresh rates. A first portion of the display operates at a higher refresh rate while a second portion operates at a lower refresh rate. This segmentation allows the display to achieve high frame rates in critical areas without requiring the entire display to run at maximum performance, thereby improving overall productivity while maintaining acceptable reliability across the full display area.
2Measurement precision
If data lines are not properly configured, then the display can still operate, but data loading accuracy decreases and capacitive coupling artifacts increase
Solution Approach 1:
Dummy data lines are introduced as intermediary elements between functional data lines. These dummy lines act as shields that reduce capacitive coupling between adjacent data lines, thereby decreasing capacitive coupling artifacts and improving data loading accuracy. The dummy lines are configured to mirror the layout of functional data lines and are driven with appropriate signals to minimize their impact on display performance.
3Productivity
If all data lines are driven simultaneously, then data can be loaded to all pixels, but capacitive coupling effects increase and data loading accuracy decreases
Solution Approach 1:
The data loading process is segmented into multiple phases, with different sets of data lines being driven at different times. By dividing the data lines into groups and staggering their drive timing, the patent reduces simultaneous switching noise and capacitive coupling effects while maintaining efficient data loading across the entire display.
Solution Approach 2:
Data lines are driven in periodic waves rather than all at once. The driver circuitry applies data signals in a sequential, periodic manner across different data line groups, which reduces peak current demands and minimizes capacitive coupling artifacts while ensuring all pixels receive their data within the required time window.
Data Source
AI summary
A display may have rows and columns of pixels. Gate lines may be used to supply gate signals to rows of the pixels. Data lines may be used to supply data signals to columns of the pixels. The data lines may include alternating even and odd data lines. Data lines may be organized in pairs each of which includes one of the odd data lines and an adjacent one of the even data lines. Demultiplexer circuitry may be configured dynamically during data loading and pixel sensing operations. During data loading, data from display driver circuitry may be supplied, alternately to odd pairs of the data lines and even pairs of the data lines. During sensing, the demultiplexer circuitry may couple a pair of the even data lines to sensing circuitry in the display driver circuitry and then may couple a pair of the odd data lines to the sensing circuitry.