Dynamic Die Mapping in Stacked Memory Architecture
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Solution Overview
Problem
Current semiconductor memory systems face challenges in reducing cost and energy consumption while maintaining high performance, particularly in the dynamic assignment of memory array die and CMOS die for optimal memory operations.
Innovation Solution
The technology involves vertically stacking memory array die and CMOS die connected via through-silicon via (TSV) connections, with a die mapping control circuit dynamically assigning support circuitry die to memory array die based on availability and performance metrics to optimize read and write operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If memory array die and CMOS die are vertically stacked with fixed assignments, then device integration is achieved, but memory system flexibility and adaptability are reduced
Solution Approach 1:
The patent implements dynamic die mapping that allows the memory system to reconfigure which CMOS die are assigned to which memory array die based on real-time performance metrics and operational conditions. This dynamic reassignment mechanism enables the system to adapt to varying workloads and hardware states, resolving the contradiction between flexibility and complexity by introducing controlled adaptability through a management circuit.
Solution Approach 2:
The system changes operational parameters by adjusting the mapping relationships between CMOS die and memory array die based on measured performance metrics such as read/write speeds and error rates. This parameter-based reconfiguration allows the system to optimize performance without requiring complete redesign of the stacked architecture, balancing adaptability with manageable complexity.
2Productivity
If multiple CMOS die are assigned to each memory array die, then memory operation performance is improved, but energy consumption increases
Solution Approach 1:
The patent applies partial action by assigning only the necessary number of CMOS die to each memory array die based on actual performance requirements rather than always using all available CMOS die. The die mapping circuit dynamically determines the optimal subset of CMOS die to activate, enabling the system to achieve sufficient throughput while minimizing energy consumption by keeping unused CMOS die in low-power states.
Solution Approach 2:
The stacked die architecture enables universal resource sharing where CMOS die can be dynamically assigned to different memory array die based on workload demands. This multi-functional assignment allows the same CMOS die to serve different memory arrays at different times, improving overall system productivity while reducing the need for dedicated high-power configurations for each memory array.
3Adaptability or versatility
If dynamic die mapping is implemented, then memory system adaptability is improved, but control circuit complexity increases
Solution Approach 1:
The die mapping circuit operates autonomously by monitoring performance metrics and automatically reconfiguring die assignments without requiring external control logic. This self-service mechanism reduces the burden on host processors and minimizes the complexity of external control circuits while maintaining high adaptability through automated decision-making based on real-time system state.
Solution Approach 2:
The system incorporates feedback loops where performance metrics from memory operations are continuously monitored and fed back to the die mapping circuit. This feedback mechanism enables the mapping circuit to make informed decisions about die reassignment, improving adaptability while keeping control complexity manageable through rule-based or algorithmic decision-making rather than complex control logic.
Data Source
AI summary
Systems and methods for dynamically assigning memory array die to CMOS die of a plurality of stacked die during memory operations are described. The plurality of stacked die may be vertically stacked and connected together via one or more vertical through-silicon via (TSV) connections. The memory array die may only comprise memory cell structures (e.g., vertical NAND strings) without column decoders, row decoders, charge pumps, sense amplifiers, control circuitry, page registers, or state machines. The CMOS die may contain support circuitry necessary for performing the memory operations, such as read and write memory operations. The one or more vertical TSV connections may allow each memory array die of the plurality of stacked die to communicate with or be electrically connected to one or more CMOS die of the plurality of stacked die.