Dynamic Divide-by-2 Circuit for 25% Duty I-Q Waveforms
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Solution Overview
Problem
Frequency dividers with 25% duty cycles face high power consumption when generating waveforms with good phase and gain accuracy.
Innovation Solution
A frequency divider circuit with a divider stage and an input stage, where output signals from the divider stage are coupled to actuate additional active components in the input stage, ensuring that each component is periodically in an ON state while another is in an OFF state, reducing power consumption by periodically turning off components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If frequency divider operates with all active components continuously enabled to maintain good phase and gain accuracy, then waveform accuracy is improved, but power consumption increases
Solution Approach 1:
The patent implements periodic switching of active components in the input stage based on the phase of the input signal. Specifically, components are enabled during certain phases (e.g., when signal is high or low) and disabled during other phases, creating a periodic on-off pattern that reduces average power consumption while maintaining waveform accuracy during active periods
Solution Approach 2:
The patent dynamically adjusts the state of active components based on real-time signal conditions. The input stage components are selectively enabled or disabled according to the instantaneous phase of the input signal, transforming a static continuously-on configuration into a dynamic conditional configuration that optimizes both power consumption and waveform accuracy
2Loss of energy
If frequency divider uses 25% duty cycle operation to achieve good conversion loss, then conversion loss is improved, but power consumption increases due to continuous operation requirements
Solution Approach 1:
The patent applies periodic switching to the input stage components, enabling them only during specific phases of the 25% duty cycle operation. This allows the frequency divider to maintain the beneficial 25% duty cycle conversion loss characteristics while reducing the time that power-consuming components are active, thereby lowering overall power consumption
Data Source
AI summary
Disclosed are frequency dividers, methods, apparatus, and other implementations, including a frequency divider that includes at least one input line to deliver at least one signal with a first frequency, a divider stage comprising multiple divider active components to produce output signals each with a second frequency equal to substantially half the first frequency, and an input stage electrically coupled to the divider stage to enable operation of the divider stage, the input stage including multiple additional active components. Each of the output signals is electrically coupled to an input of a different corresponding component of the multiple additional active components to electrically actuate the respective different corresponding components such that each of the multiple additional active components is periodically in an ON state while during the same time at least another of the multiple additional active components of the input stage is in an OFF state.