Dynamic DMA Buffer Allocation in Unified Storage
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Solution Overview
Problem
In mobile devices and other systems, DMA engines often have underutilized local memory storage due to unequal utilization, leading to inefficient memory and power consumption, as each engine is typically identical and equipped with area and power-consuming DQ flip-flops.
Innovation Solution
A processor dynamically administers DMA buffers by determining and allocating buffer sizes for each DMA engine based on expected or actual utilization, using unified DMA storage, which can be implemented with SRAM instead of DQ flip-flops, allowing for reallocation and efficient use of resources.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If each DMA engine is equipped with identical local memory storage using DQ flip-flops, then all DMA engines have sufficient buffer capacity, but memory area and power consumption increase significantly
Solution Approach 1:
The patent merges the local memory storage resources of multiple DMA engines into a single shared memory pool. Instead of each DMA engine having dedicated local buffers, all DMA engines access a common memory resource, which reduces total memory area while ensuring sufficient buffer capacity is available to any individual engine when needed.
Solution Approach 2:
The shared memory pool serves as a universal resource that can be accessed by any DMA engine requiring buffer storage. This multi-functional memory structure replaces multiple specialized local buffers, reducing overall area while maintaining the capability to support any DMA engine's buffer needs.
2Reliability
If each DMA engine is equipped with identical local memory storage using DQ flip-flops, then all DMA engines have sufficient buffer capacity, but power consumption increases
Solution Approach 1:
By combining multiple individual DMA engine buffers into a single shared memory pool, the patent reduces the total number of memory cells and associated control logic. This consolidation decreases the overall power consumption while maintaining adequate buffer capacity for all DMA engines through shared access.
3Reliability
If identical local memory storage is allocated to each DMA engine, then buffer availability is ensured, but memory utilization efficiency decreases
Solution Approach 1:
The patent combines individual DMA engine buffers into a shared pool that can be dynamically allocated among engines based on actual needs. This approach ensures buffer availability for any engine while improving overall memory utilization efficiency through shared resources and reduced redundancy.
Data Source
AI summary
A device includes a processor, unified DMA (‘Direct Memory Access’) storage, and a number of DMA engines. The processor may be operatively coupled to the unified DMA storage and a main memory. The DMA engines may be configured to access the unified DMA storage and provide DMA transmissions between the main memory and a corresponding component. The processor may be configured to: determine a size of a corresponding DMA buffer to be allocated for each DMA engine; allocate, for each DMA engine, the corresponding DMA buffer of the determined size in the unified DMA storage; and execute DMA transmission using the DMA engines and the corresponding DMA buffers.