Dynamic DMA Mapping with Standard and Huge Memory Pages
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Solution Overview
Problem
Existing systems face performance issues and security risks due to the use of single virtual addresses for multiple DMA requests, leading to inefficient translation and potential data corruption.
Innovation Solution
Dynamic selection of page sizes for virtual-to-physical address mapping, using synchronous and asynchronous mapping types to manage DMA requests, with synchronous mapping for standard pages and asynchronous mapping for huge pages, allowing batched translations and controlled invalidation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single virtual address is used for multiple DMA requests, then device complexity is reduced, but translation performance deteriorates and data security is compromised
Solution Approach 1:
The patent segments the address mapping process into two distinct types: synchronous mapping (using standard pages) and asynchronous mapping (using huge pages). This segmentation allows the system to optimize for different performance requirements independently, resolving the contradiction between simplicity and translation performance.
Solution Approach 2:
The patent introduces dynamic selection of page sizes based on the mapping type. The system can dynamically choose between standard pages and huge pages depending on the DMA request characteristics, enabling optimal translation performance while maintaining manageable complexity through structured decision logic.
2Device complexity
If a single virtual address is used for multiple DMA requests, then device complexity is reduced, but data security and stability deteriorate
Solution Approach 1:
By segmenting mappings into synchronous and asynchronous types with distinct page size requirements, the patent prevents incorrect memory access patterns. This segmentation ensures that each DMA request receives appropriate page size treatment, maintaining data stability while avoiding the complexity of fully dynamic address translation.
Solution Approach 2:
The patent changes the parameter of page size based on mapping type rather than using a fixed single virtual address approach. This parameter change enables the system to maintain security and stability by ensuring proper memory boundaries and access rights are enforced according to the specific DMA request characteristics.
3Reliability
If synchronous mapping is used for standard pages, then data stability is maintained, but translation performance deteriorates
Solution Approach 1:
The patent applies dynamics by allowing the system to adaptively select between standard pages (for synchronous mappings requiring stability) and huge pages (for asynchronous mappings where performance is prioritized). This dynamic adaptation resolves the contradiction by matching the page size to the specific operational requirements.
4Productivity
If asynchronous mapping is used for huge pages, then translation performance is improved, but data stability and security risks increase
Solution Approach 1:
The patent segments DMA requests into synchronous and asynchronous categories, assigning different page size treatments accordingly. This segmentation ensures that huge pages are only used for asynchronous mappings where performance optimization is acceptable, while standard pages maintain stability for synchronous operations, thus resolving the contradiction through structured classification.
Data Source
AI summary
The technology disclosed herein enables receiving, by an operating system running on a host computer system, a request to map a physical address associated with a peripheral device, identifying, based on the request, a mapping type, wherein the mapping type is one of: a first mapping type or a second mapping type, mapping, based on the mapping type of the request, the physical address to a virtual address referencing a memory page having one of: a first page size or a second page size, wherein the second page size exceeds the first page size, and storing a mapping of physical address to the virtual address in an input/output memory management unit (IOMMU) page table associated with the peripheral device.