Dynamic DMA Priority Control for Imaging Data Transfer
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Solution Overview
Problem
In imaging devices, the system operation can fail due to prioritization settings for DMA requests from functional blocks with DMA buffers, leading to either concentrated or infrequent DMA transfers, which can inhibit other functional blocks' access to the DRAM, especially when priorities are set based on periods of frequent or seldom performed transfers.
Innovation Solution
A data transfer device with a DMA buffer section, buffer control sections, and buffer writing/reading control sections that manage DMA transfers by using first and second writing permission signals to store and read data sequentially across storage regions, ensuring data is transferred at a desired rate without inhibiting other functional blocks, by implementing a smoothing buffer control mechanism that adjusts transfer intervals and storage based on available buffer capacity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a high priority is set for a functional block with a DMA buffer during periods of frequent DMA transfer, then the transfer rate for that functional block is improved, but other functional blocks with lower priority are inhibited from accessing the DRAM
Solution Approach 1:
The bus arbiter dynamically changes the priority of functional blocks based on their current transfer activity status. When a functional block enters a dormant state (seldom performing DMA transfer), its priority is increased to allow other functional blocks to access the DRAM. This dynamic priority adjustment resolves the contradiction by adapting priority settings to real-time system conditions rather than using fixed priorities.
Solution Approach 2:
The bus arbiter monitors the transfer activity of each functional block and uses this feedback information to adjust priority assignments. By detecting when a functional block transitions from active to dormant state, the system can respond by changing priority levels, ensuring that DRAM access is fairly distributed while maintaining high transfer rates when needed.
2Reliability
If a low priority is set for a functional block with a DMA buffer during periods of seldom DMA transfer, then other functional blocks can access the DRAM, but the transfer rate for the low priority functional block may be insufficient
Solution Approach 1:
The priority assignment is dynamic rather than static. When a functional block is in a dormant state, it receives higher priority to ensure adequate transfer rates. When it becomes active and starts frequent transfers, its priority is automatically reduced to allow other blocks to access the DRAM. This dynamic adjustment ensures both reliability and productivity are maintained under different operating conditions.
Solution Approach 2:
The system changes the priority parameter of functional blocks based on their transfer activity. By monitoring transfer frequency and adjusting the priority parameter accordingly, the system can optimize both the transfer rate for individual blocks and the overall system operation stability without conflict.
3Productivity
If DMA requests are successively output until the DMA buffer is full, then the transfer rate is maximized, but other functional blocks are inhibited from DMA transfer
Solution Approach 1:
The system uses periodic action by monitoring the transfer activity status of functional blocks and adjusting priorities at appropriate intervals. When a functional block transitions from active to dormant, the priority is adjusted, creating periodic opportunities for other blocks to access the DRAM while still allowing the original block to maintain high transfer rates during its active periods.
Solution Approach 2:
The bus arbiter acts as an intermediary that mediates between conflicting DMA requests from different functional blocks. It monitors the activity status of each block and uses this information to fairly allocate DRAM access rights, preventing any single block from monopolizing the bus while ensuring each block receives adequate transfer rates when needed.
Data Source
AI summary
A direct memory access (DMA) buffer section configured to store data in a plurality of storage regions in units of DMA transfers, a buffer control section configured to output a first writing permission signal for permitting the DMA transfer on the basis of presence or absence of a free storage region, a smoothing buffer control section configured to output a second writing permission signal for permitting the DMA transfer within a predetermined period, a buffer writing control section configured to execute the DMA transfer according to the first writing permission signal and the DMA transfer according to the second writing permission signal and stored the data to the free storage region, and a buffer reading control section configured to sequentially read the data for each storage region, wherein a predetermined amount of data sequentially acquired by a plurality of DMA transfers is output as a transfer unit.