Dynamic DMRS Antenna Port Indication for Lower URLLC Latency

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Solution Overview

Problem

Existing wireless communication systems face challenges in efficiently configuring antenna ports for demodulation reference signals, particularly in ultra-reliable low latency communications (URLLC), leading to suboptimal performance and increased latency.

Innovation Solution

A system and method for determining antenna port configurations based on bit-width values and DCI messages, including antenna port indications, to optimize demodulation reference signal transmission and reception.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of time

If traditional antenna port configuration methods are used, then device compatibility is maintained, but latency increases and communication efficiency deteriorates for URLLC

Engineering Contradiction:
ImprovelatencyVSAvoidconfiguration adaptability
Core Design Contradiction:
Loss of timeVSAdaptability or versatility

Solution Approach 1:

The patent implements dynamic antenna port configuration where the bit-width of the antenna port indication field is not fixed but can be adjusted based on URLLC requirements. The system dynamically selects between different bit-width values (0, 1, or 2 bits) to optimize latency while maintaining compatibility, allowing the configuration to adapt to different traffic types and channel conditions

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the parameter of antenna port indication bit-width from a fixed value to a variable parameter that can take different values (0, 1, or 2 bits). This parameter change enables the system to optimize for URLLC by using shorter bit-widths when appropriate, directly reducing the signaling overhead and latency while maintaining backward compatibility through standardized fallback behavior

Inventive Principle:
Principle #35Parameter changes

2Adaptability or versatility

If antenna port indication field is always included in DCI, then configuration flexibility is improved, but DCI message size and processing overhead increase

Engineering Contradiction:
Improveconfiguration flexibilityVSAvoidDCI message size
Core Design Contradiction:
Adaptability or versatilityVSQuantity of substance

Solution Approach 1:

The patent applies partial action by conditionally including the antenna port indication field in the DCI message based on the bit-width configuration. When the bit-width is set to 0, the field is completely omitted from the DCI message, reducing its size. When set to 1 or 2 bits, the field is included with minimal overhead. This partial inclusion strategy optimizes the balance between configuration flexibility and DCI message size

Inventive Principle:
Principle #16Partial or excessive action

Solution Approach 2:

The patent creates a universal DCI message structure that can function with different bit-width configurations for the antenna port indication field. The same DCI format can operate in multiple modes (with 0, 1, or 2 bit indications) depending on the configured bit-width value, allowing the system to adapt to different scenarios without requiring multiple specialized DCI formats

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS12402146B2System and method for DMRS antenna port indication for URLLC
Publication Date: 2025.08.26 APPLE INC
  • US12402146B2 patent drawing
  • US12402146B2 patent drawing
  • US12402146B2 patent drawing

AI summary

Systems, devices, and techniques for antenna port configuration in wireless communication systems are described. A described technique performed by a user equipment (UE) includes receiving configuration information that determines a bit-width value for an antenna port indication field of a downlink control information (DCI) format; receiving a DCI message that is in accordance with the DCI format; and determining an antenna port configuration for one or more demodulation reference signals based on the DCI message, the configuration information, and the bit-width value.